公开(公告)号：US20130010539A1

公开(公告)日：2013-01-10

申请号：US13463063

申请日：2012-05-03

申请人： Sang-Won Shim ,  Pan-Suk Kwak ,  Ki-Tae Park ,  Yoon-Hee Choi

发明人： Sang-Won Shim ,  Pan-Suk Kwak ,  Ki-Tae Park ,  Yoon-Hee Choi

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30

摘要： Disclosed is a nonvolatile memory device which includes memory blocks, a pre-decoder, and a row decoder. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals.

摘要翻译： 公开了一种非易失性存储器件，其包括存储器块，预解码器和行解码器。 每个存储块具有多个存储单元。 预解码器包括多路复用器和负电平移位器。 复用器被配置为响应于地址信号产生复用信号。 每个负电平移位器被配置为通过将具有接地电压的多路复用信号转换成具有第一负电压的转换多路复用信号来生成与各个多路复用信号相对应的转换的复用信号。 行解码器被配置为响应于转换的复用信号来选择至少一个存储器块。

公开(公告)号：US09431062B2

公开(公告)日：2016-08-30

申请号：US14567652

申请日：2014-12-11

申请人： Sang-Won Park ,  Kitae Park ,  Sang-Won Shim

发明人： Sang-Won Park ,  Kitae Park ,  Sang-Won Shim

IPC分类号： G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32 ,  G11C5/02 ,  G11C8/08 ,  G11C7/04 ,  G11C11/56 ,  G11C16/04

CPC分类号： G11C8/08 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32

摘要： A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a direction perpendicular to a substrate and connected between bit lines and a common source line. The method includes applying an offset pulse to a word line for a predetermined time to shorten a word line setting time, and applying a target pulse having a level which is higher or lower than a level of the offset pulse to the word line after the predetermined time.

摘要翻译： 字线驱动方法是用于非易失性存储器件，其包括具有多个串的多个存储块，所述多个存储块形成在与衬底垂直的方向上并连接在位线和公共源极线之间。 该方法包括将偏移脉冲施加到字线预定时间以缩短字线设置时间，并且在预定的时间之后将具有高于或低于偏移脉冲的电平的电平的目标脉冲施加到字线 时间。

公开(公告)号：US20120300527A1

公开(公告)日：2012-11-29

申请号：US13429899

申请日：2012-03-26

申请人： Sang-Won Shim ,  DongHun Kwak ,  Doosub Lee ,  ChiWeon Yoon

发明人： Sang-Won Shim ,  DongHun Kwak ,  Doosub Lee ,  ChiWeon Yoon

IPC分类号： G11C5/02

CPC分类号： G11C5/147 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3418 ,  H01L27/11582

摘要： According to example embodiments, a nonvolatile memory device includes a memory cell array including a plurality of memory cells stacked on a substrate, a plurality of word lines connected with the memory cell array, a plurality of pass voltage generators, and a voltage control circuit. The pass voltage generators each include a plurality of current paths and are configured to generate pass driving signals applied to unselected word lines of the plurality of word lines. The voltage control circuit is configured to control rising slopes of the pass driving signals generated from the plurality of pass voltage generators, based on adjusting the number of current paths in each pass voltage generator used to generate each driving signal.

摘要翻译： 根据示例性实施例，非易失性存储器件包括存储单元阵列，其包括堆叠在衬底上的多个存储单元，与存储单元阵列连接的多个字线，多个通过电压发生器和电压控制电路。 通过电压发生器各自包括多个电流路径，并且被配置为产生施加到多个字线的未选字线的通过驱动信号。 电压控制电路被配置为基于调整用于产生每个驱动信号的每个通过电压发生器中的电流路径的数量来控制从多个通过电压发生器产生的通过驱动信号的上升沿。

公开(公告)号：US20170330624A1

公开(公告)日：2017-11-16

申请号：US15433310

申请日：2017-02-15

申请人： Bong-soon Lim ,  Sang-won Shim

发明人： Bong-soon Lim ,  Sang-won Shim

IPC分类号： G11C16/04 ,  H01L27/11573 ,  H01L27/11568 ,  H01L23/528 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/30 ,  G11C16/06 ,  G11C16/24 ,  G11C16/12

CPC分类号： G11C16/0466 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/349 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A memory device has a vertical structure in which a row decoder, a page buffer, and a peripheral circuit are disposed under a memory cell array. The row decoder and the page buffer may be asymmetrically disposed. The peripheral circuit is disposed in an area where the row decoder and the page buffer are not disposed. The row decoder and the page buffer may be symmetrically disposed with respect to an interface of planes. The peripheral circuit may be disposed in an area including a part of the interface of the planes.

公开(公告)号：US20140233316A1

公开(公告)日：2014-08-21

申请号：US14060633

申请日：2013-10-23

申请人： Sang-Won Shim ,  Sang-Wan Nam ,  Kitae Park

发明人： Sang-Won Shim ,  Sang-Wan Nam ,  Kitae Park

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459

摘要： A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.

摘要翻译： 提供了一种非易失性存储器件的编程方法，其包括以多个垂直字符串中选择的一个串中的存储器单元进行编程; 确定所述非易失存储器件的工作模式是否是预脉冲模式; 当操作模式被确定为预脉冲模式时，将具有预定电平的预脉冲施加到与多个垂直线中的至少一个未选择垂直弦的串选择晶体管的栅极连接的串选择线 特定时间段的字符串; 以及对所编程的存储单元执行验证操作。

公开(公告)号：US08743617B2

公开(公告)日：2014-06-03

申请号：US13429899

申请日：2012-03-26

申请人： Sang-Won Shim ,  Dong-Hun Kwak ,  Doosub Lee ,  Chiweon Yoon

发明人： Sang-Won Shim ,  Dong-Hun Kwak ,  Doosub Lee ,  Chiweon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C5/147 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3418 ,  H01L27/11582

摘要： According to example embodiments, a nonvolatile memory device includes a memory cell array including a plurality of memory cells stacked on a substrate, a plurality of word lines connected with the memory cell array, a plurality of pass voltage generators, and a voltage control circuit. The pass voltage generators each include a plurality of current paths and are configured to generate pass driving signals applied to unselected word lines of the plurality of word lines. The voltage control circuit is configured to control rising slopes of the pass driving signals generated from the plurality of pass voltage generators, based on adjusting the number of current paths in each pass voltage generator used to generate each driving signal.

摘要翻译： 根据示例性实施例，非易失性存储器件包括存储单元阵列，其包括堆叠在衬底上的多个存储单元，与存储单元阵列连接的多个字线，多个通过电压发生器和电压控制电路。 通过电压发生器各自包括多个电流路径，并且被配置为产生施加到多个字线的未选字线的通过驱动信号。 电压控制电路被配置为基于调整用于产生每个驱动信号的每个通过电压发生器中的电流路径的数量来控制从多个通过电压发生器产生的通过驱动信号的上升沿。

公开(公告)号：US09941009B2

公开(公告)日：2018-04-10

申请号：US15433310

申请日：2017-02-15

申请人： Bong-soon Lim ,  Sang-won Shim

发明人： Bong-soon Lim ,  Sang-won Shim

IPC分类号： G11C16/02 ,  G11C16/04 ,  H01L23/528 ,  G11C16/08 ,  H01L27/11573 ,  H01L27/11568 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11582 ,  G11C16/34 ,  G11C16/30 ,  G11C16/24 ,  G11C16/12 ,  G11C16/06

CPC分类号： G11C16/0466 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/349 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A memory device has a vertical structure in which a row decoder, a page buffer, and a peripheral circuit are disposed under a memory cell array. The row decoder and the page buffer may be asymmetrically disposed. The peripheral circuit is disposed in an area where the row decoder and the page buffer are not disposed. The row decoder and the page buffer may be symmetrically disposed with respect to an interface of planes. The peripheral circuit may be disposed in an area including a part of the interface of the planes.

公开(公告)号：US09183943B2

公开(公告)日：2015-11-10

申请号：US14104406

申请日：2013-12-12

申请人： Yang-Lo Ahn ,  Sang-Wan Nam ,  Sang-Won Shim

发明人： Yang-Lo Ahn ,  Sang-Wan Nam ,  Sang-Won Shim

IPC分类号： G11C16/34

CPC分类号： G11C16/3427 ,  G11C16/3422

摘要： A vertical nonvolatile memory device which includes a plurality of cell strings formed in a direction intersecting with a substrate is provided. The vertical nonvolatile memory device is configured to apply a non-selection read voltage to at least one selection line connected to a cell string from among the plurality of cell strings. The vertical nonvolatile memory device is configured to apply the non-selection read voltage to at least one unselected word line of the cell string a desired time period after the applying of the non-selection read voltage to the at least one selection line.

摘要翻译： 提供一种垂直非易失性存储装置，其包括在与基板相交的方向上形成的多个单元串。 垂直非易失性存储器件被配置为向多个单元串中的连接到单元串的至少一个选择线施加非选择读取电压。 垂直非易失性存储器件被配置为在将非选择读取电压施加到至少一个选择线之后的所需时间周期内将非选择读取电压施加到单元串的至少一个未选择的字线。

公开(公告)号：US20150221351A1

公开(公告)日：2015-08-06

申请号：US14567652

申请日：2014-12-11

申请人： SANG-WON PARK ,  KITAE PARK ,  SANG-WON SHIM

发明人： SANG-WON PARK ,  KITAE PARK ,  SANG-WON SHIM

IPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/10 ,  G11C5/02

CPC分类号： G11C8/08 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32

摘要： A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a direction perpendicular to a substrate and connected between bit lines and a common source line. The method includes applying an offset pulse to a word line for a predetermined time to shorten a word line setting time, and applying a target pulse having a level which is higher or lower than a level of the offset pulse to the word line after the predetermined time.

摘要翻译： 字线驱动方法是用于非易失性存储器件，其包括具有多个串的多个存储块，所述多个存储块形成在与衬底垂直的方向上并连接在位线和公共源极线之间。 该方法包括将偏移脉冲施加到字线预定时间以缩短字线设置时间，并且在预定的时间之后将具有高于或低于偏移脉冲的电平的电平的目标脉冲施加到字线 时间。

公开(公告)号：US09859015B2

公开(公告)日：2018-01-02

申请号：US15251345

申请日：2016-08-30

申请人： Tae-Hyun Kim ,  Bong-Soon Lim ,  Yoon-Hee Choi ,  Sang-Won Shim

发明人： Tae-Hyun Kim ,  Bong-Soon Lim ,  Yoon-Hee Choi ,  Sang-Won Shim

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G06F11/10 ,  G11C29/52

CPC分类号： G11C16/3459 ,  G06F11/1068 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52

摘要： A memory device has a memory cell array with memory cells. A page buffer group generates page buffer signals according to a verify read result of the memory cells. A page buffer decoding unit generates a decoder output signal corresponding to the number of fail bits from the page buffer signals based on a first reference current. A slow bit counter outputs a count result corresponding to the number of fail bits from the decoder output signal based on a second reference current corresponding to M times the first reference current, where M is a positive integer. A pass/fail checking unit determines a program outcome with respect to the memory cells based on the count result and outputs a pass signal or a fail signal based on the determined program outcome.