公开(公告)号：US10032893B2

公开(公告)日：2018-07-24

申请号：US14860431

申请日：2015-09-21

Applicant: Infineon Technologies AG

Inventor： Armin Tilke ,  Claus Dahl ,  Dmitri A. Tschumakow

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423

Abstract: A bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure. The transistor further comprises an emitter region arranged on the base region.

公开(公告)号：US09679963B2

公开(公告)日：2017-06-13

申请号：US14969023

申请日：2015-12-15

Applicant: Infineon Technologies AG

Inventor： Dmitri Alex Tschumakow ,  Erhard Landgraf ,  Claus Dahl ,  Steffen Rothenhaeusser

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/0649 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/78

Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.

公开(公告)号：US09219117B2

公开(公告)日：2015-12-22

申请号：US14258073

申请日：2014-04-22

Applicant: Infineon Technologies AG

Inventor： Dmitri Alex Tschumakow ,  Erhard Landgraf ,  Claus Dahl ,  Steffen Rothenhaeusser

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/78

Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.

Abstract translation: 根据各种实施例，半导体结构可以包括：第一源极/漏极区域和第二源极/漏极区域; 设置在所述第一源极/漏极区域和所述第二源极/漏极区域之间的主体区域，所述主体区域包括芯区域和至少部分围绕所述芯部区域的至少一个边缘区域; 所述电介质区域位于所述主体区域的旁边，并且被配置为限制在所述身体区域的宽度方向上通过所述主体区域的电流，其中，所述至少一个边缘区域布置在所述芯区域和所述电介质区域之间; 以及门结构，其构造成控制所述身体区域; 其中所述栅极结构被配置为为所述体区的核心区域提供第一阈值电压，以及为所述身体区域的所述至少一个边缘区域提供第二阈值电压，其中所述第一阈值电压小于或等于所述第二阈值电压 阈值电压。

公开(公告)号：US08809952B2

公开(公告)日：2014-08-19

申请号：US13707386

申请日：2012-12-06

Applicant: Infineon Technologies AG

Inventor： Erhard Landgraf ,  Thomas Bertrams ,  Claus Dahl ,  Henning Feick ,  Andreas Pribil

IPC: H01L29/78 ,  H01L21/3065

CPC classification number: H01L29/7816 ,  H01L21/02107 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66325 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7835

Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone.

Abstract translation: 晶体管组件包括布置在半导体本体中的有源晶体管区域。 并且绝缘区域以环形方式围绕半导体主体中的有源晶体管区域。 源极区，漏极区，体区和漂移区设置在有源晶体管区域中。 源极区域和漏极区域在半导体主体的横向方向上间隔开，并且主体区域布置在源极区域和漂移区域之间，并且漂移区域布置在体区域和排出区域之间。 栅极和场电极布置在有源晶体管区域的上方。 电介质层在体区附近具有第一厚度，在漂移区附近的区域具有第二厚度。

公开(公告)号：US11195766B2

公开(公告)日：2021-12-07

申请号：US16129201

申请日：2018-09-12

Applicant: Infineon Technologies AG

Inventor： Dmitri Alex Tschumakow ,  Claus Dahl

IPC: H01L21/8249 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/06

Abstract: A method for manufacturing a combined semiconductor device. The method includes providing a semiconductor substrate, providing a protective layer or a protective layer stack in a non-CMOS area of the semiconductor substrate, wherein the non-CMOS area is portion of the semiconductor substrate reserved for a non-CMOS device, at least partially manufacturing a CMOS device in a CMOS area of the semiconductor substrate, the non-CMOS area and the CMOS area being different from each other, removing the protective layer or the protective layer stack, to expose the semiconductor substrate in the non-CMOS area, and manufacturing a non-CMOS device in the non-CMOS area of the semiconductor substrate.

公开(公告)号：US20190080966A1

公开(公告)日：2019-03-14

申请号：US16129201

申请日：2018-09-12

Applicant: Infineon Technologies AG

Inventor： Dmitri Alex Tschumakow ,  Claus Dahl

IPC: H01L21/8249 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/033

Abstract: A method for manufacturing a combined semiconductor device. The method includes providing a semiconductor substrate, providing a protective layer or a protective layer stack in a non-CMOS area of the semiconductor substrate, wherein the non-CMOS area is portion of the semiconductor substrate reserved for a non-CMOS device, at least partially manufacturing a CMOS device in a CMOS area of the semiconductor substrate, the non-CMOS area and the CMOS area being different from each other, removing the protective layer or the protective layer stack, to expose the semiconductor substrate in the non-CMOS area, and manufacturing a non-CMOS device in the non-CMOS area of the semiconductor substrate.

公开(公告)号：US20140339634A1

公开(公告)日：2014-11-20

申请号：US14321302

申请日：2014-07-01

Applicant: Infineon Technologies AG

Inventor： Erhard Landgraf ,  Thomas Bertrams ,  Claus Dahl ,  Henning Feick ,  Andreas Pribil

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/02107 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66325 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7835

Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone.

Abstract translation: 晶体管组件包括布置在半导体本体中的有源晶体管区域。 并且绝缘区域以环形方式围绕半导体主体中的有源晶体管区域。 源极区，漏极区，体区和漂移区设置在有源晶体管区域中。 源极区域和漏极区域在半导体主体的横向方向上间隔开，并且主体区域布置在源极区域和漂移区域之间，并且漂移区域布置在体区域和排出区域之间。 栅极和场电极布置在有源晶体管区域的上方。 电介质层在体区附近具有第一厚度，在漂移区附近的区域具有第二厚度。

公开(公告)号：US20130140632A1

公开(公告)日：2013-06-06

申请号：US13707386

申请日：2012-12-06

Applicant: Infineon Technologies AG

Inventor： Erhard Landgraf ,  Thomas Bertrams ,  Claus Dahl ,  Henning Feick ,  Andreas Pribil

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/02107 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66325 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7835

Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in in a region near the body zone and a second thickness in a region near the drift zone.

Abstract translation: 晶体管组件包括布置在半导体本体中的有源晶体管区域。 并且绝缘区域以环形方式围绕半导体主体中的有源晶体管区域。 源极区，漏极区，体区和漂移区设置在有源晶体管区域中。 源极区域和漏极区域在半导体主体的横向方向上间隔开，并且主体区域布置在源极区域和漂移区域之间，并且漂移区域布置在体区域和排出区域之间。 栅极和场电极布置在有源晶体管区域的上方。 电介质层在体区附近具有第一厚度，在漂移区附近的区域具有第二厚度。

公开(公告)号：US10573730B2

公开(公告)日：2020-02-25

申请号：US16017495

申请日：2018-06-25

Applicant: Infineon Technologies AG

Inventor： Armin Tilke ,  Claus Dahl ,  Dmitri Alex Tschumakow

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/45 ,  H01L29/737

Abstract: A bipolar transistor is described. In accordance with one aspect of the present invention the bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure. The transistor further comprises an emitter region arranged on the base region, wherein the emitter region is doped with dopants of the second doping type and forming a pn-junction with the base region.

公开(公告)号：US20180308961A1

公开(公告)日：2018-10-25

申请号：US16017495

申请日：2018-06-25

Applicant: Infineon Technologies AG

Inventor： Armin Tilke ,  Claus Dahl ,  Dmitri Alex Tschumakow

IPC: H01L29/732 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/04

Abstract: A bipolar transistor is described. In accordance with one aspect of the present invention the bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure. The transistor further comprises an emitter region arranged on the base region, wherein the emitter region is doped with dopants of the second doping type and forming a pn-junction with the base region.