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公开(公告)号：US09571108B2
公开(公告)日：2017-02-14
申请号：US14543783
申请日：2014-11-17
Applicant: Infineon Technologies AG
Inventor： Roberto Nonis , Nicola DaDalt , Edwin Thaller
CPC classification number: H03L7/085 , H03K2005/00058 , H03L7/091 , H03L7/0991 , H03L7/18
Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.
Abstract translation: 设备和技术的代表性实现提供两个信号之间的相位差的多位二进制表示。 多位二进制表示可以包括关于相位差的符号和相位差的大小的信息。
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公开(公告)号：US11233520B2
公开(公告)日：2022-01-25
申请号：US17073181
申请日：2020-10-16
Applicant: Infineon Technologies AG , Politecnico Di Milano
Inventor： Dmytro Cherniak , Salvatore Levantino , Marc Tiebout , Roberto Nonis
Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.
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公开(公告)号：US10826508B2
公开(公告)日：2020-11-03
申请号：US16189949
申请日：2018-11-13
Applicant: Infineon Technologies AG , Politecnico Di Milano
Inventor： Dmytro Cherniak , Salvatore Levantino , Marc Tiebout , Roberto Nonis
Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
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公开(公告)号：US09148101B2
公开(公告)日：2015-09-29
申请号：US13752575
申请日：2013-01-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Roberto Nonis , Nicola Da Dalt
CPC classification number: H03G1/0005 , H03K3/0315 , H03K3/354 , Y10T307/406
Abstract: At least one implementation relates to a method that includes receiving a bias voltage provided by a low-dropout voltage regulator (LDO) error amplifier; supplying a feedback voltage to the LDO error amplifier; supplying a power signal to a load; and providing a control signal to enable or disable the load and enable or disable the LDO error amplifier.
Abstract translation: 至少一个实现涉及一种包括接收由低压差稳压器（LDO）误差放大器提供的偏置电压的方法; 向LDO误差放大器提供反馈电压; 向负载提供电力信号; 并提供控制信号以启用或禁用负载，并使能或禁用LDO误差放大器。
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公开(公告)号：US20210036710A1
公开(公告)日：2021-02-04
申请号：US17073181
申请日：2020-10-16
Applicant: Infineon Technologies AG , Politecnico Di Milano
Inventor： Dmytro Cherniak , Salvatore Levantino , Marc Tiebout , Roberto Nonis
Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.
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Patent Agency Ranking
公开(公告)号：US20180241406A1
公开(公告)日：2018-08-23
申请号：US15438438
申请日：2017-02-21
Applicant: Infineon Technologies AG , Politecnico Di Milano
Inventor： Dmytro Cherniak , Salvatore Levantino , Marc Tiebout , Roberto Nonis
CPC classification number: H03L7/24 , H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/124 , H03B2201/0208 , H03L7/0991
Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
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公开(公告)号：US20190081633A1
公开(公告)日：2019-03-14
申请号：US16189949
申请日：2018-11-13
Applicant: Infineon Technologies AG , Politecnico Di Milano
Inventor： Dmytro Cherniak , Salvatore Levantino , Marc Tiebout , Roberto Nonis
CPC classification number: H03L7/24 , H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/124 , H03B2201/0208 , H03L7/093 , H03L7/0991 , H03L7/197 , H03L2207/50
Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
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公开(公告)号：US09258110B2
公开(公告)日：2016-02-09
申请号：US14266785
申请日：2014-04-30
Applicant: Infineon Technologies AG
Inventor： Werner Grollitsch , Roberto Nonis
CPC classification number: H04L7/0331 , H03L7/091 , H03L7/1806 , H03L7/1976 , H04L7/0054
Abstract: A phase detector device having a modulo N operator coupled with an adder is disclosed. Furthermore, clock recovery devices using such a phase detector device are discussed.
Abstract translation: 公开了一种具有与加法器耦合的模N运算符的相位检测器装置。 此外，讨论了使用这种相位检测器装置的时钟恢复装置。
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公开(公告)号：US20150070060A1
公开(公告)日：2015-03-12
申请号：US14543783
申请日：2014-11-17
Applicant: Infineon Technologies AG
Inventor： Roberto Nonis , Nicola DaDalt , Edwin Thaller
CPC classification number: H03L7/085 , H03K2005/00058 , H03L7/091 , H03L7/0991 , H03L7/18
Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.
Abstract translation: 设备和技术的代表性实现提供两个信号之间的相位差的多位二进制表示。 多位二进制表示可以包括关于相位差的符号和相位差的大小的信息。
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公开(公告)号：US10135452B2
公开(公告)日：2018-11-20
申请号：US15438438
申请日：2017-02-21
Applicant: Infineon Technologies AG , Politecnico Di Milano
Inventor： Dmytro Cherniak , Salvatore Levantino , Marc Tiebout , Roberto Nonis
Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
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