公开(公告)号：US10665705B2

公开(公告)日：2020-05-26

申请号：US16289166

申请日：2019-02-28

Applicant: Infineon Technologies AG

Inventor： Thomas Wuebben ,  Peter Irsigler ,  Hans-Joachim Schulze

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/223 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L29/36

Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.

公开(公告)号：US10263101B2

公开(公告)日：2019-04-16

申请号：US15295109

申请日：2016-10-17

Applicant: Infineon Technologies AG

Inventor： Thomas Wuebben ,  Peter Irsigler ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L29/739

Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.

公开(公告)号：US20200224326A1

公开(公告)日：2020-07-16

申请号：US16830603

申请日：2020-03-26

Applicant: Infineon Technologies AG

Inventor： Johannes Freund ,  Thomas Wuebben ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: C30B15/04 ,  B28D5/00 ,  C30B15/02 ,  H01L29/739 ,  C30B15/10 ,  C30B29/06 ,  C30B33/00 ,  B28D5/04 ,  H01L21/66 ,  H01L29/66

Abstract: One example describes a method of manufacturing Czochralski (CZ) silicon wafers. The method includes slicing an n-type CZ silicon ingot to form a plurality of CZ silicon wafers, determining a boron concentration of each CZ silicon wafer, dividing the CZ silicon wafers into sub-groups based on the boron concentration, wherein an average value of the boron concentration differs among the sub-groups, and labeling each sub-group of CZ silicon wafers with a different label which is indicative of the boron concentration.

公开(公告)号：US20180005831A1

公开(公告)日：2018-01-04

申请号：US15635358

申请日：2017-06-28

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Peter Irsigler ,  Thomas Wuebben

IPC: H01L21/265 ,  H01L21/324 ,  H01L29/36 ,  H01L29/06 ,  H01L29/868 ,  H01L29/78

CPC classification number: H01L21/26526 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66136 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/868

Abstract: A method includes kicking out impurity atoms from substitutional sites of a crystal lattice of a semiconductor body by implanting particles via a first surface into the semiconductor body, reducing a thickness of the semiconductor body by removing semiconductor material of the semiconductor body, and annealing the semiconductor body in a first annealing process at a temperature of between 300° C. and 450° C. to diffuse impurity atoms out of the semiconductor body.

公开(公告)号：US20180002826A1

公开(公告)日：2018-01-04

申请号：US15636926

申请日：2017-06-29

Applicant: Infineon Technologies AG

Inventor： Johannes Freund ,  Thomas Wuebben ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: C30B15/04 ,  B28D5/04 ,  H01L21/66 ,  H01L29/66

CPC classification number: C30B15/04 ,  B28D5/00 ,  B28D5/04 ,  C30B15/02 ,  H01L22/14 ,  H01L22/20 ,  H01L29/66325 ,  H01L29/7393

Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.

公开(公告)号：US10724149B2

公开(公告)日：2020-07-28

申请号：US16369419

申请日：2019-03-29

Applicant: Infineon Technologies AG

Inventor： Johannes Freund ,  Thomas Wuebben ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: C30B15/04 ,  C30B15/02 ,  B28D5/00 ,  H01L29/739 ,  C30B15/10 ,  C30B29/06 ,  C30B33/00 ,  B28D5/04 ,  H01L21/66 ,  H01L29/66

Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.

公开(公告)号：US10607839B2

公开(公告)日：2020-03-31

申请号：US15635358

申请日：2017-06-28

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Peter Irsigler ,  Thomas Wuebben

IPC: H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/36 ,  H01L29/78 ,  H01L29/868 ,  H01L29/66 ,  H01L29/32 ,  H01L21/263

Abstract: A method includes kicking out impurity atoms from substitutional sites of a crystal lattice of a semiconductor body by implanting particles via a first surface into the semiconductor body, reducing a thickness of the semiconductor body by removing semiconductor material of the semiconductor body, and annealing the semiconductor body in a first annealing process at a temperature of between 300° C. and 450° C. to diffuse impurity atoms out of the semiconductor body.

公开(公告)号：US20190249330A1

公开(公告)日：2019-08-15

申请号：US16369419

申请日：2019-03-29

Applicant: Infineon Technologies AG

Inventor： Johannes Freund ,  Thomas Wuebben ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: C30B15/04 ,  C30B15/02 ,  B28D5/00 ,  H01L29/739 ,  B28D5/04 ,  H01L29/66 ,  H01L21/66

Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.

公开(公告)号：US10273597B2

公开(公告)日：2019-04-30

申请号：US15636926

申请日：2017-06-29

Applicant: Infineon Technologies AG

Inventor： Johannes Freund ,  Thomas Wuebben ,  Helmut Oefner ,  Hans-Joachim Schulze

IPC: C30B15/04 ,  H01L29/66 ,  B28D5/04 ,  B28D5/00 ,  C30B15/02 ,  H01L21/66 ,  H01L29/739

Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.