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    LOW POWER BUFFER WITH GAIN BOOST
    2.
    发明申请
    LOW POWER BUFFER WITH GAIN BOOST 有权
    低功耗缓冲器与增压

    公开(公告)号：US20160352372A1

    公开(公告)日：2016-12-01

    申请号：US15231449

    申请日：2016-08-08

    Applicant: INPHI CORPORATION

    Inventor： James Lawrence GORECKI ,  Han-Yuan TAN

    IPC: H04B1/16 ,  H03K5/02 ,  H03M1/12 ,  H03K3/012

    CPC classification number: H03K5/023 ,  G11C27/026 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/45475 ,  H03G3/20 ,  H03K3/012 ,  H03M1/1215 ,  H03M1/124 ,  H03M3/38 ,  H04B17/21

    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

    Abstract translation: 本公开提供了用于实现具有增益提升的低功率缓冲器的技术的详细描述。 更具体地，本公开的一些实施例涉及具有堆叠晶体管配置的缓冲器，其中第一晶体管接收输入信号，并且第二晶体管接收输入信号的补码。 第一晶体管被配置为产生对输入信号的非反相响应，并且第二晶体管被配置为产生对输入信号的补码的反相响应，并且产生负gds效应，使缓冲器显示为低 功率和单位增益在宽带宽。 在其他实施例中，堆叠晶体管配置可以部署在完全不同的实现中。 在其他实施例中，缓冲器可以包括用于改善线性度，DC电平偏移，电容性输入负载以及输出回转，稳定和驱动能力的技术。

    LOW POWER BUFFER WITH GAIN BOOST
    3.
    发明申请
    LOW POWER BUFFER WITH GAIN BOOST 审中-公开

    公开(公告)号：US20170207864A1

    公开(公告)日：2017-07-20

    申请号：US15476645

    申请日：2017-03-31

    Applicant: INPHI CORPORATION

    Inventor： James Lawrence GORECKI ,  Han-Yuan TAN

    IPC: H04B17/21 ,  H03M3/00 ,  H03G3/20 ,  H03M1/12 ,  H03K3/012 ,  H03K5/02

    CPC classification number: H03K5/023 ,  G11C27/026 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/45475 ,  H03G3/20 ,  H03K3/012 ,  H03M1/1215 ,  H03M1/124 ,  H03M3/38 ,  H04B17/21

    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

    WIDEBAND LOW DROPOUT VOLTAGE REGULATOR WITH POWER SUPPLY REJECTION BOOST
    5.
    发明申请
    WIDEBAND LOW DROPOUT VOLTAGE REGULATOR WITH POWER SUPPLY REJECTION BOOST 有权

    公开(公告)号：US20170126329A1

    公开(公告)日：2017-05-04

    申请号：US15374983

    申请日：2016-12-09

    Applicant: INPHI CORPORATION

    Inventor： James Lawrence GORECKI ,  Han-Yuan TAN

    IPC: H04B10/69 ,  G05F1/575

    CPC classification number: G05F1/565 ,  G05F1/575

    Abstract: The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.

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