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    Series continuous time linear equalizers
    1.
    发明授权
    Series continuous time linear equalizers 有权

    公开(公告)号：US10658016B1

    公开(公告)日：2020-05-19

    申请号：US16214480

    申请日：2018-12-10

    Applicant: Integrated Device Technology, Inc.

    Inventor： David Chang

    IPC: G11C7/10

    Abstract: An apparatus includes a first continuous time linear equalizer circuit and a second continuous time linear equalizer circuit. The first continuous time linear equalizer circuit may be configured to generate an intermediate signal by filtering an input signal using a first passive bandpass filter having an inductor. The second continuous time linear equalizer circuit may be configured to generate an output signal by filtering the intermediate signal.

    LOW POWER DELAY BUFFER BETWEEN EQUALIZER AND HIGH SENSITIVITY SLICER
    2.
    发明申请
    LOW POWER DELAY BUFFER BETWEEN EQUALIZER AND HIGH SENSITIVITY SLICER 审中-公开

    公开(公告)号：US20200075084A1

    公开(公告)日：2020-03-05

    申请号：US16565913

    申请日：2019-09-10

    Applicant: Integrated Device Technology, Inc.

    Inventor： David Chang

    IPC: G11C11/4093 ,  G11C11/4076

    Abstract: An apparatus includes a continuous-time linear equalizer circuit, a buffer and at least one slicer. The continuous-time linear equalizer circuit may be configured to generate a first intermediate signal by equalizing an input signal relative to a reference voltage. The input signal may be single-ended. The first intermediate signal may be differential. The buffer may be configured to generate a second intermediate signal by delaying the first intermediate signal. The second intermediate signal may be differential. The slicer may be configured to generate an output signal by slicing the second intermediate signal. The output signal may be single-ended.

    Open loop solution in data buffer and RCD
    3.
    发明授权
    Open loop solution in data buffer and RCD 有权

    公开(公告)号：US10437279B2

    公开(公告)日：2019-10-08

    申请号：US16194657

    申请日：2018-11-19

    Applicant: Integrated Device Technology, Inc.

    Inventor： David Chang ,  Xudong Shi

    IPC: G06F1/10 ,  H03K5/05 ,  G11C7/22 ,  H03L7/08 ,  G06F1/08 ,  G11C29/02 ,  G11C5/04 ,  G11C29/00 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/10

    Abstract: An apparatus includes a clock tree circuit, a first phase interpolator circuit and a second phase interpolator circuit. The clock tree circuit may be configured to generate a first clock delayed from a system clock by a constant time. The first phase interpolator circuit may be in a calibration loop and configured to generate a second clock with a programmable phase delay relative to the first clock. The programmable phase delay may be controlled by a control value. The calibration loop may be configured to determine the control value that results in a given delay between the system clock and the second clock. The second phase interpolator circuit may be in a normal signal path and configured to generate a third clock with the given delay relative to the first clock using the control value such that the third clock is offset from the system clock by the given delay.

    Low power delay buffer between equalizer and high sensitivity slicer
    5.
    发明授权
    Low power delay buffer between equalizer and high sensitivity slicer 有权

    公开(公告)号：US10475506B1

    公开(公告)日：2019-11-12

    申请号：US16117230

    申请日：2018-08-30

    Applicant: Integrated Device Technology, Inc.

    Inventor： David Chang

    IPC: G11C11/40 ,  G11C11/4093 ,  G11C11/4076

    Abstract: An apparatus includes a continuous-time linear equalizer circuit, a buffer and at least one slicer. The continuous-time linear equalizer circuit may be configured to generate a first intermediate signal by equalizing an input signal relative to a reference voltage. The input signal may be single-ended. The first intermediate signal may be differential. The buffer may be configured to generate a second intermediate signal by delaying the first intermediate signal. The second intermediate signal may be differential. The slicer may be configured to generate an output signal by slicing the second intermediate signal. The output signal may be single-ended.

    Open loop solution in data buffer and RCD
    6.
    发明授权
    Open loop solution in data buffer and RCD 有权

    公开(公告)号：US10409320B2

    公开(公告)日：2019-09-10

    申请号：US16106119

    申请日：2018-08-21

    Applicant: Integrated Device Technology, Inc.

    Inventor： David Chang ,  Xudong Shi

    IPC: G06F1/10 ,  G06F1/08 ,  H03K5/05 ,  G11C7/22 ,  H03L7/08 ,  G11C5/04 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  H03L7/081 ,  H03L7/07

    Abstract: An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.

    Low power delay buffer between equalizer and high sensitivity slicer
    8.
    发明授权
    Low power delay buffer between equalizer and high sensitivity slicer 有权

    公开(公告)号：US10665293B2

    公开(公告)日：2020-05-26

    申请号：US16565913

    申请日：2019-09-10

    Applicant: Integrated Device Technology, Inc.

    Inventor： David Chang

    IPC: G11C11/40 ,  G11C11/4093 ,  G11C11/4076

    Abstract: An apparatus includes a continuous-time linear equalizer circuit, a buffer and at least one slicer. The continuous-time linear equalizer circuit may be configured to generate a first intermediate signal by equalizing an input signal relative to a reference voltage. The input signal may be single-ended. The first intermediate signal may be differential. The buffer may be configured to generate a second intermediate signal by delaying the first intermediate signal. The second intermediate signal may be differential. The slicer may be configured to generate an output signal by slicing the second intermediate signal. The output signal may be single-ended.

    Resynchronization of a clock associated with each data bit in a double data rate memory system
    9.
    发明授权
    Resynchronization of a clock associated with each data bit in a double data rate memory system 有权

    公开(公告)号：US10241538B2

    公开(公告)日：2019-03-26

    申请号：US15439190

    申请日：2017-02-22

    Applicant: Integrated Device Technology, Inc.

    Inventor： David Chang ,  Xudong Shi ,  Shubing Zhai ,  Chenxiao Ren

    IPC: G06F1/12 ,  G06F1/10 ,  G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22 ,  G06F13/16

    Abstract: An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.

    SERIES CONTINUOUS TIME LINEAR EQUALIZERS
    10.
    发明申请
    SERIES CONTINUOUS TIME LINEAR EQUALIZERS 审中-公开

    公开(公告)号：US20200185013A1

    公开(公告)日：2020-06-11

    申请号：US16214480

    申请日：2018-12-10

    Applicant: Integrated Device Technology, Inc.

    Inventor： David Chang

    IPC: G11C7/10

    Abstract: An apparatus includes a first continuous time linear equalizer circuit and a second continuous time linear equalizer circuit. The first continuous time linear equalizer circuit may be configured to generate an intermediate signal by filtering an input signal using a first passive bandpass filter having an inductor. The second continuous time linear equalizer circuit may be configured to generate an output signal by filtering the intermediate signal.

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