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    Fractional reference-injection PLL
    2.
    发明授权
    Fractional reference-injection PLL 有权
    小数参考注入PLL

    公开(公告)号：US09369139B1

    公开(公告)日：2016-06-14

    申请号：US14622851

    申请日：2015-02-14

    Applicant: Integrated Device Technology, Inc.

    Inventor： Min Chu ,  Jagdeep Bal

    IPC: H03K3/03 ,  H03L3/00 ,  H03L7/099

    CPC classification number: H03L7/0995 ,  H03B2200/009 ,  H03B2200/0094 ,  H03B2200/0096 ,  H03K3/013 ,  H03K3/0315 ,  H03L3/00 ,  H03L7/081 ,  H03L7/183 ,  H03L2207/06

    Abstract: Methods and apparatuses are described to reduce phase noise in a low noise fractional reference-injection phase locked loop (FRIPLL). The FRIPLL includes a ring voltage controlled oscillator (VCO). An output of the ring VCO is input to a fractional interpolative frequency divider (FIFD). A signal comparison circuit receives a reference clock signal and a further delayed output of the FIFD. The signal comparison circuit produces a control voltage signal in response to a phase difference between the reference clock signal and the further delayed output of the FIFD. The control voltage signal is input to the ring VCO to control a ring VCO frequency. An oscillator control circuit has a first input and a second input. The first input is a first delayed output of the FIFD. The second input is the reference clock signal. The oscillator control circuit generates a realignment signal which is used to realign a state transition in a ring VCO output signal to the reference clock signal when the ring VCO output signal is in a low state. Realignment occurs repeatedly at a frequency of the reference clock signal.

    Abstract translation: 描述了在低噪声分数参考 - 注入锁相环（FRIPLL）中减少相位噪声的方法和装置。 FRIPLL包括一个环形压控振荡器（VCO）。 环形VCO的输出被输入到分数内插分频器（FIFD）。 信号比较电路接收FIFD的参考时钟信号和进一步延迟的输出。 信号比较电路响应于参考时钟信号和FIFD的进一步延迟输出之间的相位差产生控制电压信号。 控制电压信号被输入到环形VCO以控制环形VCO频率。 振荡器控制电路具有第一输入和第二输入。 第一个输入是FIFD的第一个延迟输出。 第二个输入是参考时钟信号。 当环形VCO输出信号处于低电平状态时，振荡器控制电路产生一个重新对准信号，该对准信号用于将环形VCO输出信号中的状态转换重新对准基准时钟信号。 在参考时钟信号的频率处重复对准。

    Calibration method and apparatus for phase locked loop circuit
    3.
    发明授权
    Calibration method and apparatus for phase locked loop circuit 有权

    公开(公告)号：US09654121B1

    公开(公告)日：2017-05-16

    申请号：US15169997

    申请日：2016-06-01

    Applicant: Integrated Device Technology, Inc.

    Inventor： Min Chu

    IPC: H03L7/06 ,  H03L7/099

    CPC classification number: H03L7/0992 ,  H03L7/099 ,  H03L2207/06 ,  H03L2207/50

    Abstract: An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, includes a calibration circuit. The calibration circuit is coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator. The calibration circuit includes a counting circuit for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal. The calibration circuit also includes a selection block for performing a convergence test using the counted number of fast clock cycles, N, and M. The selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band.

    High-speed programmable frequency divider with 50% output duty cycle
    4.
    发明授权
    High-speed programmable frequency divider with 50% output duty cycle 有权
    高速可编程分频器，占空比为50％

    公开(公告)号：US09590637B1

    公开(公告)日：2017-03-07

    申请号：US14839817

    申请日：2015-08-28

    Applicant: Integrated Device Technology, Inc.

    Inventor： Pak-Kim Lau ,  Min Chu

    IPC: H03K21/00 ,  H03K23/40 ,  H03K23/66 ,  H03K21/10

    CPC classification number: H03K23/40 ,  H03K21/10 ,  H03K23/66

    Abstract: A frequency divider includes a multiplexer having a first input terminal coupled to receive a first value M and a second input terminal for receiving a second value that is M+LSB, the multiplexer is configured to alternately output the first value M and the second value. The frequency divider includes a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles. A divide-by-two counter having an input coupled to the output of the multi-modulus divider, is operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency of N, where N is equal to 2M+LSB. Duty cycle correction logic is coupled to the output of the divide-by-two counter and is configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when N is odd.

    Abstract translation: 分频器包括多路复用器，其具有耦合以接收第一值M的第一输入端和用于接收作为M + LSB的第二值的第二输入端，所述多路复用器被配置为交替地输出第一值M和第二值。 分频器包括耦合到多路复用器的多模式分频器，用于接收多路复用器的输出，该多模除法器可操作以在M个输入时钟周期和M + LSB时钟周期交替地产生输出脉冲。 具有耦合到多模式分频器的输出的输入的二分频计数器可操作以分频多模式分频器的输出，以产生频率为N的分频时钟信号，其中N等于 2M + LSB。 占空比校正逻辑耦合到二分频计数器的输出，并且被配置为当N为奇数时将分频时钟信号的占空比校正为百分之五十占空比。

    Buffer with programmable input/output phase relationship
    6.
    发明授权
    Buffer with programmable input/output phase relationship 有权

    公开(公告)号：US09859901B1

    公开(公告)日：2018-01-02

    申请号：US15064369

    申请日：2016-03-08

    Applicant: Integrated Device Technology, Inc.

    Inventor： Min Chu ,  John C. Hsu ,  Ron D. Wade

    IPC: H03L7/06 ,  H03L7/081 ,  H03L7/091

    CPC classification number: H03L7/081 ,  H03L7/085

    Abstract: An apparatus includes a phase locked loop circuit having a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator. The apparatus includes at least one delay element disposed so as to enable contributing at least one of the following: i) delay to a signal provided to the first input of the phase comparator; ii) delay to a signal provided to the second input of the phase comparator. A delay contributed by the at least one delay element varies in accordance with an associated delay control value. The phase locked loop circuit and the at least one delay element reside on a same semiconductor substrate.

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