公开(公告)号：US20240282667A1

公开(公告)日：2024-08-22

申请号：US18635894

申请日：2024-04-15

Applicant: Intel Corporation

Inventor： Weston BERTRAND ,  Kyle ARRINGTON ,  Shankar DEVASENATHIPATHY ,  Aaron MCCANN ,  Nicholas NEAL ,  Zhimin WAN

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/433 ,  H01L23/3675 ,  H01L25/0657

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20210257277A1

公开(公告)日：2021-08-19

申请号：US16794789

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Weston BERTRAND ,  Kyle ARRINGTON ,  Shankar DEVASENATHIPATHY ,  Aaron MCCANN ,  Nicholas NEAL ,  Zhimin WAN

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20230128903A1

公开(公告)日：2023-04-27

申请号：US18088478

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Weston BERTRAND ,  Kyle ARRINGTON ,  Shankar DEVASENATHIPATHY ,  Aaron MCCANN ,  Nicholas NEAL ,  Zhimin WAN

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/367

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20200043894A1

公开(公告)日：2020-02-06

申请号：US16051065

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： George VAKANAS ,  Aastha UPPAL ,  Shereen ELHALAWATY ,  Aaron MCCANN ,  Edvin CETEGEN ,  Tannaz HARIRCHIAN ,  Saikumar JAYARAMAN

IPC: H01L25/065 ,  H01L27/108 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

公开(公告)号：US20210272885A1

公开(公告)日：2021-09-02

申请号：US16803887

申请日：2020-02-27

Applicant: Intel Corporation

Inventor： Kyle ARRINGTON ,  Aaron MCCANN ,  Weston K. BERTRAND

IPC: H01L23/495 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and an interposer over the package substrate. In an embodiment, the interposer comprises a ceramic. In an embodiment, the electronic package further comprises a first die over the interposer and a second die over the interposer. In an embodiment, the first die and the second die are electrically coupled together by the interposer. In an embodiment, the electronic package further comprises an integrated heat spreader (IHS) over the first die and the second die.

公开(公告)号：US20210195798A1

公开(公告)日：2021-06-24

申请号：US16723865

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Nicholas NEAL ,  Nicholas S. HAEHN ,  Je-Young CHANG ,  Kyle ARRINGTON ,  Aaron MCCANN ,  Edvin CETEGEN ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN ,  Ken P. HACKENBERG ,  Sergio A. CHAN ARGUEDAS

IPC: H05K7/20 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.