公开(公告)号：US09935191B2

公开(公告)日：2018-04-03

申请号：US15122627

申请日：2014-06-13

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Sansaptak Dasgupta ,  Alejandro X. Levander ,  Patrick Morrow

IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L21/78 ,  H01L29/04 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/76254 ,  H01L21/7806 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

公开(公告)号：US10439057B2

公开(公告)日：2019-10-08

申请号：US15329216

申请日：2014-09-09

Applicant: INTEL CORPORATION

Inventor： Kimin Jun ,  Sansaptak Dasgupta ,  Alejandro X. Levander ,  Patrick Morrow

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/66 ,  H01L21/762

Abstract: A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.

公开(公告)号：US09548320B2

公开(公告)日：2017-01-17

申请号：US14930171

申请日：2015-11-02

Applicant: INTEL CORPORATION

Inventor： Alejandro X. Levander ,  Kimin Jun

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/12 ,  H01L21/762 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/06 ,  H01L29/26

CPC classification number: H01L27/1207 ,  H01L21/02002 ,  H01L21/02521 ,  H01L21/02634 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/265 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76251 ,  H01L21/76254 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/26

Abstract: Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands.

Abstract translation: 公开了在初始衬底上的晶格失配的半导体材料层的异质外延生长的技术，以及将该层的无缺陷部分转移到处理晶片或其它合适的衬底以进行集成。 根据一些实施例，转移可能导致在手柄晶片/衬底上存在岛状氧化物结构，每个具有嵌入其上表面内的晶格失配的半导体材料的无缺陷岛。 每个无缺陷的半导体岛可以具有一个或多个晶面的边缘，并且随着其伴随的氧化物结构可提供用于集成的平坦表面。 在一些情况下，第二不同的半导体材料的层可以在手柄晶片/衬底上异质外延生长以填充转移的岛周围的区域。 在一些其它情况下，处理晶片/衬底本身可以被同侧外延生长以填充转移的岛周围的区域。

公开(公告)号：US09177967B2

公开(公告)日：2015-11-03

申请号：US14139954

申请日：2013-12-24

Applicant: Intel Corporation

Inventor： Alejandro X. Levander ,  Kimin Jun

IPC: H01L27/00 ,  H01L21/00 ,  H01L27/12 ,  H01L21/762 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L27/1207 ,  H01L21/02002 ,  H01L21/02521 ,  H01L21/02634 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/265 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76251 ,  H01L21/76254 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/26

Abstract: Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands.

Abstract translation: 公开了在初始衬底上的晶格失配的半导体材料层的异质外延生长的技术，以及将该层的无缺陷部分转移到处理晶片或其它合适的衬底以进行集成。 根据一些实施例，转移可能导致在手柄晶片/衬底上存在岛状氧化物结构，每个具有嵌入其上表面内的晶格失配的半导体材料的无缺陷岛。 每个无缺陷的半导体岛可以具有一个或多个晶面的边缘，并且随着其伴随的氧化物结构可提供用于集成的平坦表面。 在一些情况下，第二不同的半导体材料的层可以在手柄晶片/衬底上异质外延生长以填充转移的岛周围的区域。 在一些其它情况下，处理晶片/衬底本身可以被同侧外延生长以填充转移的岛周围的区域。