公开(公告)号：US20180096737A1

公开(公告)日：2018-04-05

申请号：US15282574

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Wei Ming Lim ,  Madhu Rao ,  Alvin Shing Chye Goh ,  Kim Leong Lee ,  Terrence Huat Hin Tan ,  Vui Yong Liew ,  Yah Chen Chew

IPC: G11C29/56 ,  G06F1/10

CPC classification number: G11C29/56004 ,  G06F1/10 ,  G11C29/56012 ,  G11C2029/5602

Abstract: Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.

公开(公告)号：US12093195B2

公开(公告)日：2024-09-17

申请号：US18134920

申请日：2023-04-14

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Steven T. Taylor ,  Alvin Shing Chye Goh

IPC: G06F12/00 ,  G06F9/30 ,  G06F13/16 ,  G06F13/42 ,  G06F18/214 ,  G11C7/10 ,  G11C7/22 ,  H03M13/09

CPC classification number: G06F13/1689 ,  G06F9/30029 ,  G06F13/4243 ,  G06F18/214 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/222 ,  H03M13/09

Abstract: Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.

公开(公告)号：US10236076B2

公开(公告)日：2019-03-19

申请号：US15282574

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Wei Ming Lim ,  Madhu Rao ,  Alvin Shing Chye Goh ,  Kim Leong Lee ,  Terrence Huat Hin Tan ,  Vui Yong Liew ,  Yah Chen Chew

IPC: G06F1/10 ,  G11C29/56

Abstract: Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to hold the plurality of read request commands while a hold signal has a first value, and to sequentially release individual read request commands of the plurality of read request commands while to the hold signal has a second value. The digital controller further to provide input/output (I/O) commands to an output based on a particular released read request command of the plurality of read request commands. Timing of provision of the I/O commands is deterministic based on a transition of the hold signal from the first value to the second value.

公开(公告)号：US11675716B2

公开(公告)日：2023-06-13

申请号：US16709798

申请日：2019-12-10

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Steven T. Taylor ,  Alvin Shing Chye Goh

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G06F9/30 ,  G11C7/10 ,  G11C7/22 ,  H03M13/09 ,  G06F18/214

CPC classification number: G06F13/1689 ,  G06F9/30029 ,  G06F13/4243 ,  G06F18/214 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/222 ,  H03M13/09

Abstract: Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.