公开(公告)号：US20170336978A1

公开(公告)日：2017-11-23

申请号：US15618170

申请日：2017-06-09

Applicant: Intel Corporation

Inventor： BLAISE FANNING ,  MARK A. SCHMISSEUR ,  RAYMOND S. TETRICK ,  ROBERT J. ROYER, JR. ,  DAVID B. MINTURN ,  SHANE MATTHEWS

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F13/28

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0644 ,  G06F3/0664 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/28 ,  G06F2212/7206

Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

公开(公告)号：US20170177502A1

公开(公告)日：2017-06-22

申请号：US14975752

申请日：2015-12-19

Applicant: Intel Corporation

Inventor： DANIEL GREENSPAN ,  BLAISE FANNING ,  YOAV LOSSIN ,  ASAF RUBINSTEIN

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/123 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/60 ,  Y02D10/13

Abstract: A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment of the invention comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy with respect to the first entry.

公开(公告)号：US20160203864A1

公开(公告)日：2016-07-14

申请号：US14879008

申请日：2015-10-08

Applicant: Intel Corporation

Inventor： SHEKOUFEH QAWAMI ,  RAJESH SUNDARAM ,  DAVID J. ZIMMERMAN ,  BLAISE FANNING

IPC: G11C13/00

CPC classification number: G11C13/0038 ,  G06F1/3275 ,  G06F9/30101 ,  G06F12/0246 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/06 ,  Y02D10/14

Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.