公开(公告)号：US20210098373A1

公开(公告)日：2021-04-01

申请号：US16583691

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Juan G. ALZATE VINASCO ,  Chieh-Jen KU ,  Shem O. OGADHOH ,  Allen B. GARDINER ,  Blake C. LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

公开(公告)号：US20200020378A1

公开(公告)日：2020-01-16

申请号：US16565299

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Liqiong WEI ,  Fatih HAMZAOGLU ,  Yih WANG ,  Nathaniel J. AUGUST ,  Blake C. LIN ,  Cyrille DRAY

IPC: G11C11/16 ,  G11C13/00 ,  G11C29/02

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US20180342277A1

公开(公告)日：2018-11-29

申请号：US16052552

申请日：2018-08-01

Applicant: Intel Corporation

Inventor： Liqiong WEI ,  Fatih HAMZAOGLU ,  Yih WANG ,  Nathaniel J. AUGUST ,  Blake C. LIN ,  Cyrille DRAY

IPC: G11C11/16 ,  G11C13/00 ,  G11C29/02

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1677 ,  G11C11/1693 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2213/74 ,  G11C2213/79

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US20160125927A1

公开(公告)日：2016-05-05

申请号：US14129277

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Liqiong WEI ,  Fatih HAMZAOGLU ,  Yih WANG ,  Nathaniel J. AUGUST ,  Blake C. LIN ,  Cyrille DRAY

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1677 ,  G11C11/1693 ,  G11C13/00 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2213/74 ,  G11C2213/79

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

Abstract translation: 描述了用于提高电阻式存储器能量效率的装置。 一种装置执行数据驱动写入，以利用write0和write1操作之间的非对称写入开关能量。 该装置包括：耦合到位线和选择线的电阻存储器单元; 耦合到位线的第一通过栅极; 耦合到所述选择线的第二通过栅极; 以及可由输入数据操作的多路复用器，用于根据输入数据的逻辑电平向第一和第二传递门提供控制信号或写入驱动器。 一种装置包括用于在写入操作之前执行读取的电路，其避免了利用初始低功率读取操作的不必要的写入。 一种装置包括执行自动写入操作的电路，其一旦位单元翻转就停止写入操作。 一种装置包括用于执行自动读取操作的电路，其在检测到数据时停止读取操作。