公开(公告)号：US20040222512A1

公开(公告)日：2004-11-11

申请号：US10869176

申请日：2004-06-16

Applicant: INTEL CORPORATION

Inventor： Boyd L. Coomer

IPC: H01L021/44 ,  H01L021/8242 ,  H01L023/02 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L24/82 ,  H01L24/24 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82103 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method and system for electrically interconnecting a semiconductor device and a component is presented. The semiconductor device includes a dielectric portion on at least one face thereof. Similarly, the component includes a dielectric portion on at least one face thereof The device and component are constructed and arranged to be stacked and bonded together. A first laser selectively ablates the respective dielectric portions of the device and component. The ablating creates a starting pad on the device or component and a destination pad on the device or component. A second laser deposits a conductor along a path between the starting pad and destination pad. As such, smaller, more condensed electronic packages may be fabricated.

Abstract translation: 提出了一种用于电连接半导体器件和部件的方法和系统。 半导体器件在其至少一个面上包括电介质部分。 类似地，该部件在其至少一个面上包括电介质部分。该器件和部件被构造和布置成堆叠并结合在一起。 第一激光器选择性地烧蚀器件和部件的相应电介质部分。 消融在设备或组件上创建启动焊盘，并在设备或组件上创建目标焊盘。 第二激光器沿着起始焊盘和目的地焊盘之间的路径沉积导体。 因此，可以制造更小，更浓缩的电子封装。

公开(公告)号：US20040118594A1

公开(公告)日：2004-06-24

申请号：US10323165

申请日：2002-12-18

Applicant: Intel Corporation

Inventor： Thomas S. Dory ,  Michael Walk ,  Robert L. Sankman ,  Boyd L. Coomer

IPC: H05K003/20 ,  H05K001/11

CPC classification number: H05K3/107 ,  H05K3/0014 ,  H05K3/005 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: To decrease the complexity, time, and cost of fabricating an electronics package, and to potentially increase the quality and decrease the size thereof, the package includes at least one electronic component mounted on an imprinted substrate. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Such features may be formed by imprinting in one operation rather than sequentially. Conductor features, such as trenches, holes, and planes, may be formed of different sizes simultaneously. Methods of fabrication, as well as application of the imprinted package to an electronic assembly, are also described.

Abstract translation: 为了降低制造电子封装的复杂性，时间和成本，并且潜在地提高质量并减小其尺寸，封装包括安装在压印基板上的至少一个电子部件。 在一个实施例中，衬底可以包括导电迹线，通路和一个或多个层上的焊盘图案。 这些特征可以通过在一个操作中打印而不是顺序地形成。 诸如沟槽，孔和平面的导体特征可以同时由不同尺寸形成。 还描述了制造方法以及将印刷包装应用于电子组件。