公开(公告)号：US20040118604A1

公开(公告)日：2004-06-24

申请号：US10322902

申请日：2002-12-18

Applicant: Intel Corporation

Inventor： Thomas S. Dory ,  Michael Walk

IPC: H05K001/11

CPC classification number: H05K3/107 ,  H05K1/0373 ,  H05K3/0014 ,  H05K3/005 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1189 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: To decrease the complexity, time, and cost of fabricating an electronics package, and to potentially increase the quality and decrease the size thereof, the package includes at least one electronic component mounted on a substrate formed through imprinting. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Conductor features of different geometries may be formed by imprinting them simultaneously on one or both surfaces of an imprintable tape. Fabrication apparatus and methods, as well as application of the imprinted package to an electronic assembly, are also described.

Abstract translation: 为了降低制造电子封装的复杂性，时间和成本，并且潜在地提高质量并减小其尺寸，封装包括安装在通过压印形成的衬底上的至少一个电子部件。 在一个实施例中，衬底可以包括导电迹线，通路和一个或多个层上的焊盘图案。 不同几何形状的导体特征可以通过将它们同时压印在可压印带的一个或两个表面上而形成。 还描述了制造装置和方法，以及将压印包装应用于电子组件。

公开(公告)号：US20040118594A1

公开(公告)日：2004-06-24

申请号：US10323165

申请日：2002-12-18

Applicant: Intel Corporation

Inventor： Thomas S. Dory ,  Michael Walk ,  Robert L. Sankman ,  Boyd L. Coomer

IPC: H05K003/20 ,  H05K001/11

CPC classification number: H05K3/107 ,  H05K3/0014 ,  H05K3/005 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: To decrease the complexity, time, and cost of fabricating an electronics package, and to potentially increase the quality and decrease the size thereof, the package includes at least one electronic component mounted on an imprinted substrate. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Such features may be formed by imprinting in one operation rather than sequentially. Conductor features, such as trenches, holes, and planes, may be formed of different sizes simultaneously. Methods of fabrication, as well as application of the imprinted package to an electronic assembly, are also described.

Abstract translation: 为了降低制造电子封装的复杂性，时间和成本，并且潜在地提高质量并减小其尺寸，封装包括安装在压印基板上的至少一个电子部件。 在一个实施例中，衬底可以包括导电迹线，通路和一个或多个层上的焊盘图案。 这些特征可以通过在一个操作中打印而不是顺序地形成。 诸如沟槽，孔和平面的导体特征可以同时由不同尺寸形成。 还描述了制造方法以及将印刷包装应用于电子组件。

公开(公告)号：US20020075630A1

公开(公告)日：2002-06-20

申请号：US09741302

申请日：2000-12-19

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Huong T. Do ,  Jorge Pedro Rodriguez ,  Michael Walk

IPC: H01G002/20

CPC classification number: H01G2/065 ,  H01L2924/15311

Abstract: A capacitor (FIGS. 6-9) includes one or more extended surface lands (604, 704, 804, 904, FIGS. 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, FIG. 6) of the capacitor or 20% of the length (914, FIG. 9) of the capacitor. When embedded within an integrated circuit package (1102, FIG. 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).

Abstract translation: 电容器（图6-9）包括一个或多个延伸的表面焊盘（604,704,804,904，图6-9）。 在一个实施例中，每个延伸的表面焊盘是电容器的顶部或底部表面上的焊盘，其具有等于电容器的宽度（614，图6）的至少30％的平台长度或20％ 电容器的长度（914，图9）。 当嵌入在集成电路封装（1102，图11）中时，两个或更多个通孔（1112）可以电连接到扩展表面焊盘（1108）。