公开(公告)号：US20040238942A1

公开(公告)日：2004-12-02

申请号：US10884644

申请日：2004-07-02

Applicant: Intel Corporation

Inventor： Kishore K. Chakravorty ,  Paul H. Wermer ,  David G. Figueroa ,  Debabrata Gupta

IPC: H01L023/48 ,  H01L029/40

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/0306 ,  H05K1/141 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/09309 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.