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    LOW-LATENCY INTERNODE COMMUNICATION
    2.
    发明申请
    LOW-LATENCY INTERNODE COMMUNICATION 有权

    公开(公告)号：US20170091003A1

    公开(公告)日：2017-03-30

    申请号：US14866955

    申请日：2015-09-26

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Joseph Murray

    IPC: G06F9/54 ,  G06F13/42 ,  G06F13/24

    CPC classification number: G06F9/546 ,  G06F13/24 ,  G06F13/4282

    Abstract: A low-latency internode messaging scheme bypasses the nodes' I/O stacks to use fabrics or links that support memory process logic (e.g., SMI3) or electrical process logic (e.g., PCIe) on the “node side” between the nodes and a pooled memory controller (or pooled storage controller), and on the “pooled side” between that controller and its pooled memory or storage. The controller may translate and redirect messages and look up addresses. The approaches accommodate 2-level memory (locally attached node memory and accessible pooled memory) with either or both levels private, globally shared, allocated to a subset of the nodes, or any combination. Compatible interrupt schema use the messaging links and components.

    SIDEBAND PARITY HANDLING
    3.
    发明申请
    SIDEBAND PARITY HANDLING 有权
    旁边的尊严处理

    公开(公告)号：US20160182186A1

    公开(公告)日：2016-06-23

    申请号：US14578313

    申请日：2014-12-19

    Applicant: Intel Corporation

    Inventor： Robert P. Adler ,  Geetani R. Edirisooriya ,  Joseph Murray ,  Deep K. Buch

    IPC: H04L1/00

    CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L12/40 ,  H04L12/40045 ,  H04L2001/0094

    Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

    Abstract translation: 提供入站边带接口以通过第一边带链路接收消息，并且提供奇偶校验逻辑以计算消息的奇偶校验位。 此外，提供出站边带接口以通过第二边带链路将消息转发到另一设备。 第二边带链路包括多条数据线和奇偶位线。 消息通过至少一些数据线转发，并且奇偶校验位通过奇偶校验位线发送到另一设备以对应于消息。

    Issuing Requests To A Fabric
    5.
    发明申请
    Issuing Requests To A Fabric 审中-公开
    向织物发出请求

    公开(公告)号：US20150113189A1

    公开(公告)日：2015-04-23

    申请号：US14578720

    申请日：2014-12-22

    Applicant: Intel Corporation

    Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Kar Leong Wong ,  Robert P. Adler

    IPC: G06F13/42 ,  G06F13/368

    CPC classification number: G06F13/4221 ,  G06F13/366 ,  G06F13/368 ,  G06F13/4022 ,  G06F15/7807 ,  G06F15/7864

    Abstract: In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，一种方法包括确定是否已经通过结构从源代理发送到目标代理的第一事务已经满足生产者 - 消费者排序规则，并且如果是，则从第一事务发送第一事务的第一请求 源代理程序在第一个时钟周期。 然后，可以以流水线的方式从源代理向结构发送第二请求用于第二事务。 描述和要求保护其他实施例。

    Low-latency internode communication
    7.
    发明授权
    Low-latency internode communication 有权

    公开(公告)号：US09665415B2

    公开(公告)日：2017-05-30

    申请号：US14866955

    申请日：2015-09-26

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Joseph Murray

    IPC: G06F13/00 ,  G06F9/54 ,  G06F13/24 ,  G06F13/42

    CPC classification number: G06F9/546 ,  G06F13/24 ,  G06F13/4282

    Abstract: A low-latency internode messaging scheme bypasses the nodes' I/O stacks to use fabrics or links that support memory process logic (e.g., SMI3) or electrical process logic (e.g., PCIe) on the “node side” between the nodes and a pooled memory controller (or pooled storage controller), and on the “pooled side” between that controller and its pooled memory or storage. The controller may translate and redirect messages and look up addresses. The approaches accommodate 2-level memory (locally attached node memory and accessible pooled memory) with either or both levels private, globally shared, allocated to a subset of the nodes, or any combination. Compatible interrupt schema use the messaging links and components.

    Supporting multiple channels of a single interface
    10.
    发明授权
    Supporting multiple channels of a single interface 有权
    支持单个接口的多个通道

    公开(公告)号：US09489329B2

    公开(公告)日：2016-11-08

    申请号：US14209146

    申请日：2014-03-13

    Applicant: INTEL CORPORATION

    Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Eran Tamari ,  Joseph Murray ,  Rohit R. Verma

    IPC: G06F13/36 ,  G06F13/00 ,  G06F13/364 ,  G06F13/362 ,  G06F15/16 ,  G06F9/44

    CPC classification number: G06F13/364 ,  G06F9/44 ,  G06F13/362 ,  G06F15/16

    Abstract: In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于从结构中的第一代理接收对交易的请求并获得交易的地址，请求者标识符，标签和业务类别的方法，以及确定 基于至少两个地址，请求者标识符，标签和流量类来接收交易的目标代理。 基于此通道确定，可以将事务发送到目标代理的通道。 描述和要求保护其他实施例。

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