公开(公告)号：US11486923B2

公开(公告)日：2022-11-01

申请号：US16210259

申请日：2018-12-05

Applicant: Intel Corporation

Inventor： Jagat Shakya ,  Ethan Caughey ,  Jeremy Alan Streifer

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/00 ,  G01R31/26 ,  G01R31/28

Abstract: Disclosed herein are apparatuses and methods for mitigating sticking of units-under-test (UUTs). For example, in some embodiments, a probe card may include a probe landing pad, a guide plate having a hole therein, and a pushing mechanism. The pushing mechanism may include a pusher needle and a pusher needle support, the pusher needle support may be between the probe landing pad and the guide plate, and the pusher needle support may be controllable to cause the pusher needle to extend and retract through the hole in the guide plate.

公开(公告)号：US20200182928A1

公开(公告)日：2020-06-11

申请号：US16210259

申请日：2018-12-05

Applicant: Intel Corporation

Inventor： Jagat Shakya ,  Ethan Caughey ,  Jeremy Alan Streifer

IPC: G01R31/28 ,  G01R1/067

Abstract: Disclosed herein are apparatuses and methods for mitigating sticking of units-under-test (UUTs). For example, in some embodiments, a probe card may include a probe landing pad, a guide plate having a hole therein, and a pushing mechanism. The pushing mechanism may include a pusher needle and a pusher needle support, the pusher needle support may be between the probe landing pad and the guide plate, and the pusher needle support may be controllable to cause the pusher needle to extend and retract through the hole in the guide plate.

公开(公告)号：US12163982B2

公开(公告)日：2024-12-10

申请号：US17709487

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Jagat Shakya ,  Ethan Caughey ,  Joseph Parks, Jr.

IPC: G01R1/073 ,  G01R1/02 ,  G01R1/04 ,  G01R1/067 ,  G01R31/26 ,  G01R31/28 ,  G01R35/00

Abstract: The present disclosure is directed to an inspection tool having a probe head with a probe card with a plurality of probes for performing testing, each of the probes being configured with a first end attached to the probe card and a second end for engaging microbumps coupled to a semiconductor die, the plurality of probes including a first set of probes having a first cross-sectional dimension, the first set of probes being arranged in a first set of locations on the probe card, and a second set of probes having a second cross-sectional dimension, the second set of probes being arranged in a second set of locations on the probe card, and a stage for holding the semiconductor die.

公开(公告)号：US11740282B1

公开(公告)日：2023-08-29

申请号：US17709483

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Jagat Shakya ,  Joseph Parks, Jr. ,  Ethan Caughey ,  Ashwin Ashok ,  Prasanna Thiyagasundaram

IPC: G01R31/20 ,  G01R31/28 ,  G01R1/073 ,  G01R1/04

CPC classification number: G01R31/2891 ,  G01R1/0483 ,  G01R1/07314 ,  G01R31/2853 ,  G01R31/2886 ,  G01R31/2887 ,  H01L2924/00 ,  H01L2924/01006 ,  H01L2924/01033

Abstract: An apparatus includes an input probe configured to be placed on a first cluster of u-bumps disposed on a semiconductor die, output probes configured to be respectively placed on multiple clusters of u-bumps disposed on the semiconductor die, the multiple clusters being separately connected to the first cluster. The apparatus further includes a space transformer and printed circuit board (PCB) portion including a current source configured to supply a current to the input probe placed on the first cluster, resistors having a same resistance and being connected to ground, and tester channels at which voltages are respectively measured, the tester channels being respectively connected to ends of the output probes respectively placed on the multiple clusters and being respectively connected to the resistors. The apparatus further includes a processor configured to determine whether the input probe is properly aligned with the first cluster, based on the measured voltages.

公开(公告)号：US10429439B2

公开(公告)日：2019-10-01

申请号：US15201315

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  J. Daniel Bryan ,  Joseph W. Parks, Jr. ,  Ethan Caughey ,  Mark W. Dryfuse

IPC: G01R31/28 ,  G01R31/26 ,  H01L23/538 ,  G01R1/073

Abstract: An apparatus for testing a die can comprise a first printed circuit board (PCB), a space transformer, and a plurality of probes. The first PCB can be configured to connect to a second PCB. The space transformer can be attached to the PCB. The space transformer can include a plurality of traces. Each of the plurality of probes can be connected to one of the plurality of traces.