公开(公告)号：US20190155780A1

公开(公告)日：2019-05-23

申请号：US16258429

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Tsu-Chien HSUEH ,  Ganesh BALAMURUGAN ,  Bryan K. Casper

IPC: G06F13/40 ,  G06F1/18 ,  G06F1/3296 ,  G06F1/3287 ,  H04L25/02 ,  G06F13/36

CPC classification number: G06F13/4072 ,  G06F1/189 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/20 ,  G06F13/36 ,  G06F13/4282 ,  H04L25/0272

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

公开(公告)号：US20200328915A1

公开(公告)日：2020-10-15

申请号：US16305116

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： Aruna KUMAR ,  Anoop KARUNAN ,  Ganesh BALAMURUGAN ,  Prakash RADHAKRISHNAN

IPC: H04L25/02 ,  H04L25/03 ,  H04L25/08 ,  H04L1/24 ,  H04L7/10

Abstract: Disclosed herein are devices and methods to facilitate compensating for intra-pair skew in a high-definition multimedia interface (HDMI) system. One or more skew training pattern may be transmitted on a signal line including a differential pair. Acknowledgment of receiving the skew training pattern may be received on a display data channel (DDC) associated with HDMI system. The skew training pattern may be used to ascertain and compensate for intra-pair skew.

公开(公告)号：US20170168969A1

公开(公告)日：2017-06-15

申请号：US15440568

申请日：2017-02-23

Applicant: Intel Corporation

Inventor： Tsu-Chien HSUEH ,  Ganesh BALAMURUGAN ,  Bryan K. Casper

IPC: G06F13/36 ,  G06F1/32 ,  G06F13/40

CPC classification number: G06F13/4072 ,  G06F1/189 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/20 ,  G06F13/36 ,  G06F13/4282 ,  H04L25/0272

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

公开(公告)号：US20160241249A1

公开(公告)日：2016-08-18

申请号：US15025226

申请日：2013-11-19

Applicant: INTEL CORPORATION

Inventor： Ganesh BALAMURUGAN ,  Mozhgan MANSURI ,  Sami HYVONEN ,  Bryan K. CASPER ,  Frank O'MAHONY

IPC: H03L7/00 ,  H04B1/04 ,  H03K5/156 ,  H04L25/03

CPC classification number: H03L7/00 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/08 ,  H04B1/04 ,  H04L25/03

Abstract: Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.

Abstract translation: 描述了一种装置，其包括：异步时钟发生器，用于产生异步时钟信号; 数字采样器，用于使用异步时钟信号对信号进行采样; 用于接收差分输入时钟并产生差分输出时钟的占空比校正器（DCC），其中所述数字采样器从所述差分输出时钟采样至少一个输出时钟; 以及计数器来计数数字采样器的输出，并向DCC提供控制以调整差分输出时钟的占空比。