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公开(公告)号：US20170329727A1
公开(公告)日：2017-11-16
申请号：US15608846
申请日：2017-05-30
Applicant: Intel Corporation
Inventor： Christopher P. MOZAK , James A. McCALL , Bryan K. CASPER
CPC classification number: G06F13/1657 , G06F11/10 , G06F13/4004 , G06F13/4022 , G06F13/4072 , G06F13/4217 , G06F13/4221 , G06F13/4234 , H04L25/4915 , Y02D10/14 , Y02D10/151
Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.
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公开(公告)号：US20190121754A1
公开(公告)日：2019-04-25
申请号：US16028137
申请日：2018-07-05
Applicant: Intel Corporation
Inventor： Christopher P. MOZAK , James A. McCALL , Bryan K. CASPER
CPC classification number: G06F13/1657 , G06F11/10 , G06F13/4004 , G06F13/4022 , G06F13/4072 , G06F13/4217 , G06F13/4221 , G06F13/4234 , H04L25/4915 , Y02D10/14 , Y02D10/151
Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.
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公开(公告)号：US20220155539A1
公开(公告)日：2022-05-19
申请号：US16953146
申请日：2020-11-19
Applicant: Intel Corporation
Inventor： Srinivas V. PIETAMBARAM , Brandon C. MARIN , Sameer PAITAL , Sai VADLAMANI , Rahul N. MANEPALLI , Xiaoqian LI , Suresh V. POTHUKUCHI , Sujit SHARAN , Arnab SARKAR , Omkar KARHADE , Nitin DESHPANDE , Divya PRATAP , Jeremy ECTON , Debendra MALLIK , Ravindranath V. MAHAJAN , Zhichao ZHANG , Kemal AYGÜN , Bai NIE , Kristof DARMAWIKARTA , James E. JAUSSI , Jason M. GAMBA , Bryan K. CASPER , Gang DUAN , Rajesh INTI , Mozhgan MANSURI , Susheel JADHAV , Kenneth BROWN , Ankar AGRAWAL , Priyanka DOBRIYAL
IPC: G02B6/42
Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.
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Patent Agency Ranking
公开(公告)号：US20180232275A1
公开(公告)日：2018-08-16
申请号：US15889082
申请日：2018-02-05
Applicant: Intel Corporation
Inventor： Bryan K. CASPER , Stephen R. Mooney , David Dunning , Mozhgan Mansuri , James E. Jaussi
CPC classification number: G06F11/1076 , G11C5/02 , G11C29/12 , H01L2224/16145 , H03M13/15 , H03M13/152
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
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公开(公告)号：US20160241249A1
公开(公告)日：2016-08-18
申请号：US15025226
申请日：2013-11-19
Applicant: INTEL CORPORATION
Inventor： Ganesh BALAMURUGAN , Mozhgan MANSURI , Sami HYVONEN , Bryan K. CASPER , Frank O'MAHONY
CPC classification number: H03L7/00 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , H03K5/1565 , H03L7/08 , H04B1/04 , H04L25/03
Abstract: Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.
Abstract translation: 描述了一种装置，其包括：异步时钟发生器，用于产生异步时钟信号; 数字采样器，用于使用异步时钟信号对信号进行采样; 用于接收差分输入时钟并产生差分输出时钟的占空比校正器（DCC），其中所述数字采样器从所述差分输出时钟采样至少一个输出时钟; 以及计数器来计数数字采样器的输出，并向DCC提供控制以调整差分输出时钟的占空比。
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公开(公告)号：US20200233746A1
公开(公告)日：2020-07-23
申请号：US16844925
申请日：2020-04-09
Applicant: Intel Corporation
Inventor： Bryan K. CASPER , Stephen R. Mooney , David Dunning , Mozhgan Mansuri , James E. Jaussi
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
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公开(公告)号：US20200081852A1
公开(公告)日：2020-03-12
申请号：US16546210
申请日：2019-08-20
Applicant: Intel Corporation
Inventor： Christopher P. MOZAK , James A. McCALL , Bryan K. CASPER
Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.
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公开(公告)号：US20190354437A1
公开(公告)日：2019-11-21
申请号：US16529716
申请日：2019-08-01
Applicant: Intel Corporation
Inventor： Bryan K. CASPER , Stephen R. Mooney , David Dunning , Mozhgan Mansuri , James E. Jaussi
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
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