公开(公告)号：US11152352B2

公开(公告)日：2021-10-19

申请号：US16368671

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Akm Ahsan ,  Mark Armstrong ,  Guannan Liu

IPC: H01L27/02 ,  H01L21/8249 ,  H01L27/06

Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.

公开(公告)号：US20200259018A1

公开(公告)日：2020-08-13

申请号：US16270826

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Said Rami ,  Hyung-Jin Lee ,  Saurabh Morarka ,  Guannan Liu ,  Qiang Yu ,  Bernhard Sell ,  Mark Armstrong

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/40

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

公开(公告)号：US12205947B2

公开(公告)日：2025-01-21

申请号：US18207065

申请日：2023-06-07

Applicant: Intel Corporation

Inventor： Guannan Liu ,  Akm A. Ahsan ,  Mark Armstrong ,  Bernhard Sell

IPC: H01L27/07 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

公开(公告)号：US11515424B2

公开(公告)日：2022-11-29

申请号：US16270826

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Said Rami ,  Hyung-Jin Lee ,  Saurabh Morarka ,  Guannan Liu ,  Qiang Yu ,  Bernhard Sell ,  Mark Armstrong

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/265 ,  H01L29/165

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

公开(公告)号：US11728335B2

公开(公告)日：2023-08-15

申请号：US16257855

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Guannan Liu ,  Akm A. Ahsan ,  Mark Armstrong ,  Bernhard Sell

IPC: H01L27/07 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0705 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

公开(公告)号：US20200312838A1

公开(公告)日：2020-10-01

申请号：US16368671

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Akm Ahsan ,  Mark Armstrong ,  Guannan Liu

IPC: H01L27/02 ,  H01L27/06 ,  H01L21/8249

Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.