公开(公告)号：US11121073B2

公开(公告)日：2021-09-14

申请号：US15943565

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Travis Lajoie ,  Abhishek Sharma ,  Juan Alzate-Vinasco ,  Chieh-Jen Ku ,  Shem Ogadhoh ,  Allen Gardiner ,  Blake Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/108 ,  H01L23/532

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US20200006634A1

公开(公告)日：2020-01-02

申请号：US16024522

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Justin Brockman ,  Conor Puls ,  Stephen Wu ,  Christopher Wiegand ,  Tofizur Rahman ,  Daniel Ouellette ,  Angeline Smith ,  Andrew Smith ,  Pedro Quintero ,  Juan Alzate-Vinasco ,  Oleg Golonzka

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L21/768 ,  G11C11/16 ,  H01L27/22 ,  H01L23/528

Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.

公开(公告)号：US20190305081A1

公开(公告)日：2019-10-03

申请号：US15941557

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Travis W. LaJoie ,  Abhishek A. Sharma ,  Juan Alzate-Vinasco ,  Chieh-Jen Ku ,  Shem O. Ogadhoh ,  Allen B. Gardiner ,  Blake C. Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/764 ,  H01L21/02 ,  H01L29/423 ,  H01L27/105

Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

公开(公告)号：US12176284B2

公开(公告)日：2024-12-24

申请号：US17398933

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Travis Lajoie ,  Abhishek Sharma ,  Juan Alzate-Vinasco ,  Chieh-Jen Ku ,  Shem Ogadhoh ,  Allen Gardiner ,  Blake Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L23/522 ,  H01L23/532 ,  H01L49/02 ,  H10B12/00

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US11380838B2

公开(公告)日：2022-07-05

申请号：US16024522

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Justin Brockman ,  Conor Puls ,  Stephen Wu ,  Christopher Wiegand ,  Tofizur Rahman ,  Daniel Ouellette ,  Angeline Smith ,  Andrew Smith ,  Pedro Quintero ,  Juan Alzate-Vinasco ,  Oleg Golonzka

IPC: H01L43/02 ,  G11C11/16 ,  H01L21/768 ,  H01L23/528 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.