公开(公告)号：US11621395B2

公开(公告)日：2023-04-04

申请号：US16396465

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Nathan Strutt ,  Albert Chen ,  Pedro Quintero ,  Oleg Golonzka

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

公开(公告)号：US20200006634A1

公开(公告)日：2020-01-02

申请号：US16024522

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Justin Brockman ,  Conor Puls ,  Stephen Wu ,  Christopher Wiegand ,  Tofizur Rahman ,  Daniel Ouellette ,  Angeline Smith ,  Andrew Smith ,  Pedro Quintero ,  Juan Alzate-Vinasco ,  Oleg Golonzka

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L21/768 ,  G11C11/16 ,  H01L27/22 ,  H01L23/528

Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.

公开(公告)号：US11462684B2

公开(公告)日：2022-10-04

申请号：US16226198

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Albert Chen ,  Nathan Strutt ,  Oleg Golonzka ,  Pedro Quintero ,  Christopher J. Jezewski ,  Elijah V. Karpov

IPC: H01L45/00

Abstract: An RRAM device is disclosed. The RRAM device includes a bottom electrode, a high-k material on the bottom electrode, a top electrode, a top contact on the top electrode and an encapsulating layer of Al2O3. The encapsulating layer encapsulates the bottom electrode, the high-k material, the top electrode and the top contact.

公开(公告)号：US11380838B2

公开(公告)日：2022-07-05

申请号：US16024522

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Justin Brockman ,  Conor Puls ,  Stephen Wu ,  Christopher Wiegand ,  Tofizur Rahman ,  Daniel Ouellette ,  Angeline Smith ,  Andrew Smith ,  Pedro Quintero ,  Juan Alzate-Vinasco ,  Oleg Golonzka

IPC: H01L43/02 ,  G11C11/16 ,  H01L21/768 ,  H01L23/528 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.

公开(公告)号：US20200343445A1

公开(公告)日：2020-10-29

申请号：US16396465

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Nathan Strutt ,  Albert Chen ,  Pedro Quintero ,  Oleg Golonzka

IPC: H01L45/00 ,  G11C13/00

Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.