公开(公告)号：US20180007782A1

公开(公告)日：2018-01-04

申请号：US15201422

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： ZHICHAO ZHANG ,  XIANG LI ,  KEMAL AYGUN ,  ZHIGUO QIAN ,  TOLGA MEMIOGLU

IPC: H05K1/02 ,  G11C5/06 ,  G06F1/16 ,  G11C5/04 ,  H05K1/18 ,  H01R12/73

CPC classification number: G06F1/16 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  H01R13/6464 ,  H05K1/0231 ,  H05K1/117 ,  H05K1/141 ,  H05K1/162 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: One embodiment provides an apparatus. The apparatus includes a dual in-line memory module (DIMM). The DIMM includes at least one memory module integrated circuit (IC); a DIMM printed circuit board (PCB); a plurality of DIMM PCB contacts; and a capacitive structure. Each DIMM PCB contact is to couple the memory module IC to a respective DIMM connector pin. The capacitive structure is to provide a mutual capacitance between a first DIMM connector signal pin and a second DIMM connector signal pin.

公开(公告)号：US20180372952A1

公开(公告)日：2018-12-27

申请号：US15979382

申请日：2018-05-14

Applicant: Intel Corporation

Inventor： ZHICHAO ZHANG ,  KEMAL AYGUN ,  ROBERT L. SANKMAN

IPC: G02B6/12 ,  G02B6/42

CPC classification number: G02B6/12004 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4295 ,  G02B6/43 ,  G02B2006/12121 ,  G02B2006/12142 ,  G02B2006/12147

Abstract: Techniques and mechanisms for providing a bridge between integrated circuit (IC) chips. In an embodiment, the bridge device comprises a semiconductor substrate having disposed thereon contacts to couple the bridge device to two IC chips. Circuit structures and photonic structures of a bridge link are integrated with the substrate. The structures include an optical waveguide coupled between an electrical-to-optical signal conversion mechanism and an optical-to-electrical conversion mechanism. The bridge device converts signaling from an electrical domain to an optical domain and back to an electrical domain. In another embodiment, optical signals received via different respective contacts of an IC chip are converted by the bridge device, where the optical signals are multiplexed with each other and variously propagated with the same optical waveguide.

公开(公告)号：US20170085243A1

公开(公告)日：2017-03-23

申请号：US14860318

申请日：2015-09-21

Applicant: Intel Corporation

Inventor： BEOM-TAEK LEE ,  DHANYA ATHREYA ,  KEMAL AYGUN ,  SUBAS BASTOLA

IPC: H03H7/38

CPC classification number: H01P5/028

Abstract: One embodiment provides an apparatus. The apparatus includes an impedance matching interconnect having a first end and a second end. The impedance matching interconnect includes an interface trace having a first width at the first end and a second width at the second end, the first width less than the second width. The impedance matching interconnect further includes a first dielectric layer adjacent the interface trace; a first reference plane adjacent the first dielectric layer; at least one via adjacent the first reference plane; and a second reference plane adjacent the at least one via, the at least one via to couple the first reference plane and the second reference plane. A first distance between the interface trace and the first reference plane is less than a second distance between the interface trace and the second reference plane.

公开(公告)号：US20190295936A1

公开(公告)日：2019-09-26

申请号：US15926531

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： ZHIGUO QIAN ,  KALADHAR RADHAKRISHNAN ,  KEMAL AYGUN

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/68 ,  H01L21/48

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20170168235A1

公开(公告)日：2017-06-15

申请号：US14964426

申请日：2015-12-09

Applicant: Intel Corporation

Inventor： ZHICHAO ZHANG ,  KEMAL AYGUN ,  ROBERT L. SANKMAN

IPC: G02B6/12 ,  G02B6/42

CPC classification number: G02B6/12004 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4295 ,  G02B2006/12121 ,  G02B2006/12142 ,  G02B2006/12147

Abstract: Techniques and mechanisms for providing a bridge between integrated circuit (IC) chips. In an embodiment, the bridge device comprises a semiconductor substrate having disposed thereon contacts to couple the bridge device to two IC chips. Circuit structures and photonic structures of a bridge link are integrated with the substrate. The structures include an optical waveguide coupled between an electrical-to-optical signal conversion mechanism and an optical-to-electrical conversion mechanism. The bridge device converts signaling from an electrical domain to an optical domain and back to an electrical domain. In another embodiment, optical signals received via different respective contacts of an IC chip are converted by the bridge device, where the optical signals are multiplexed with each other and variously propagated with the same optical waveguide.