公开(公告)号：US20170085243A1

公开(公告)日：2017-03-23

申请号：US14860318

申请日：2015-09-21

Applicant: Intel Corporation

Inventor： BEOM-TAEK LEE ,  DHANYA ATHREYA ,  KEMAL AYGUN ,  SUBAS BASTOLA

IPC: H03H7/38

CPC classification number: H01P5/028

Abstract: One embodiment provides an apparatus. The apparatus includes an impedance matching interconnect having a first end and a second end. The impedance matching interconnect includes an interface trace having a first width at the first end and a second width at the second end, the first width less than the second width. The impedance matching interconnect further includes a first dielectric layer adjacent the interface trace; a first reference plane adjacent the first dielectric layer; at least one via adjacent the first reference plane; and a second reference plane adjacent the at least one via, the at least one via to couple the first reference plane and the second reference plane. A first distance between the interface trace and the first reference plane is less than a second distance between the interface trace and the second reference plane.

公开(公告)号：US20170207146A1

公开(公告)日：2017-07-20

申请号：US15036385

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： GONG OUYANG ,  BEOM-TAEK LEE

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L23/48 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/07 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2224/85399

Abstract: Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with die pads on an IC die, with an outer surface of the second insulated wire located at a distance of less than an outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location and located at a distance of less than the outer cross-sectional diameter from an outer surface of the third insulated wire at a second location. Other embodiments may be described and/or claimed.