公开(公告)号：US10120731B2

公开(公告)日：2018-11-06

申请号：US14129935

申请日：2013-07-15

Applicant: INTEL CORPORATION

Inventor： Khun Ban ,  Kingsum Chow ,  Shirish Aundhe ,  Sandhya Viswanathan

IPC: G06F12/00 ,  G06F9/52 ,  G06F9/30 ,  G06F9/38 ,  G06F8/70

Abstract: Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.

公开(公告)号：US09760404B2

公开(公告)日：2017-09-12

申请号：US14842359

申请日：2015-09-01

Applicant: Intel Corporation

Inventor： Keqiang Wu ,  Kingsum Chow ,  Ying C. Feng ,  Khun Ban

IPC: G06F9/46 ,  G06F9/50 ,  G06F1/32 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/5011 ,  G06F1/32 ,  G06F11/3006 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3442 ,  G06F11/3466 ,  G06F11/3495 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.

公开(公告)号：US20180241811A1

公开(公告)日：2018-08-23

申请号：US15439668

申请日：2017-02-22

Applicant: Intel Corporation

Inventor： Li Chen ,  Krishnaswamy Viswanathan ,  Khun Ban

IPC: H04L29/08

CPC classification number: H04L67/1012 ,  H04L67/1008

Abstract: Disclosed is a mechanism for determining incompatible co-tenants in a cloud network. Cloud performance data is received indicating resource usage of tenants operating on a per server basis. Cross-correlation analysis is performed on past resource usage for each tenant pair operating on the server to determine correlated tenant pairs. Time series forecasting of predicted resource usage is performed for each tenant in the correlated tenant pairs. Cross-correlation analysis is then performed on the predicted resource usage for each correlated tenant pair to determine incompatible co-tenant pairs. The determined incompatible co-tenant pairs may be forwarded toward an orchestration system for hardware resource allocation in the cloud network.

公开(公告)号：US10452443B2

公开(公告)日：2019-10-22

申请号：US15670525

申请日：2017-08-07

Applicant: Intel Corporation

Inventor： Keqiang Wu ,  Kingsum Chow ,  Ying Feng ,  Khun Ban

IPC: G06F9/46 ,  G06F9/50 ,  G06F1/32 ,  G06F11/34 ,  G06F11/30

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.

公开(公告)号：US09954744B2

公开(公告)日：2018-04-24

申请号：US14842438

申请日：2015-09-01

Applicant: Intel Corporation

Inventor： Keqiang Wu ,  Kingsum Chow ,  Ying Feng ,  Khun Ban ,  Zhidong Yu

IPC: H04L12/26

CPC classification number: H04L43/04 ,  H04L43/024 ,  H04L43/062 ,  H04L43/067 ,  H04L43/0817 ,  H04L43/16

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for estimation of application execution performance variations on a processor, without a priori knowledge of the application. A system may include network traffic data collection circuitry configured to sample a first network traffic statistic, from a network interface circuit associated with the processor, at a first sampling time interval during the application execution. The network traffic data collection circuitry may also be configured to sample a second network traffic statistic from the network interface circuit at a second sampling time interval during the application execution. The system may further include performance analysis circuitry configured to calculate a ratio of the first network traffic statistic to the second network traffic statistic and to estimate the application execution performance variation from the first sampling time interval to the second sampling time interval, wherein the estimation is proportional to the calculated ratio.

公开(公告)号：US09286224B2

公开(公告)日：2016-03-15

申请号：US14090056

申请日：2013-11-26

Applicant: Intel Corporation

Inventor： Seth H. Pugsley ,  Robert L. Scott ,  Zeshan A. Chishti ,  Peng-Fei Chuang ,  Khun Ban ,  Christopher B. Wilkerson ,  Shih-Lien L. Lu ,  Kingsum Chow

IPC: G06F12/08 ,  G06F9/45

CPC classification number: G06F12/0862 ,  G06F8/4442 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/602 ,  Y02D10/13

Abstract: In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括具有一个或多个执行单元的至少一个核，第一高速缓冲存储器和第一高速缓存控制逻辑。 第一高速缓存控制逻辑可以被配置为生成预取第一数据的第一预取请求，其中如果第一数据不存在于耦合到第一高速缓存存储器的第二高速缓冲存储器中，则该请求将被中止。 描述和要求保护其他实施例。

公开(公告)号：US20150220372A1

公开(公告)日：2015-08-06

申请号：US14129935

申请日：2013-07-15

Applicant: INTEL CORPORATION

Inventor： Khun Ban ,  Kingsum Chow ,  Shirish Aundhe ,  Sandhya Viswanathan

IPC: G06F9/52 ,  G06F9/44

CPC classification number: G06F9/52 ,  G06F8/70 ,  G06F9/30076 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/528

Abstract: Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及用于控制通过同时执行的代码部分来调节对共享资源的访问的锁的使用的技术。 用于控制资源锁定的装置包括处理器组件，历史分析器，用于由处理器组件执行以用锁定标记来分析替换第一代码实例的锁定指令的至少一个结果，以允许处理器组件 推测性地执行代码的第二实例，以及用于由处理器组件执行的锁定组件，以基于至少一个结果的分析，用于访问资源的代码的第一和第二实例来代替具有锁定标记的锁定指令，以及 锁定指令请求对该资源的访问锁定到第一个代码。 描述和要求保护其他实施例。