公开(公告)号：US20160093375A1

公开(公告)日：2016-03-31

申请号：US14850152

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Doyle Rivers ,  Derchang Kau ,  Matthew Goldman

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

Abstract translation: 本公开涉及交叉点存储器中的参考和感测架构。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括被配置为选择与目标存储器单元相关联的全局WL（GWL）和本地WL（LWL）的字线（WL）开关电路; 配置为选择与目标存储器单元相关联的全局BL（GBL）和本地BL（LBL）的位线（BL）开关电路; 以及感测电路，包括第一感测电路电容和第二感测电路电容，所述感测电路经配置以将所选择的GWL，LWL和第一感测电路电容预充电至WL偏置电压WLVDM，产生利用电荷的参考电压（VREF） 在所选择的GWL上并对第一感测电路电容进行充电，并且至少部分地基于VREF和检测到的存储器单元电压VLWL来确定目标存储器单元的状态。

公开(公告)号：US10268542B2

公开(公告)日：2019-04-23

申请号：US15443707

申请日：2017-02-27

Applicant: INTEL CORPORATION

Inventor： Matthew Goldman ,  Wayne D. Tran ,  Aliasgar S. Madraswala ,  Sungho Park

IPC: G06F11/00 ,  G06F11/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C29/04

Abstract: An apparatus comprises a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.

公开(公告)号：US09747978B2

公开(公告)日：2017-08-29

申请号：US14850152

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Doyle Rivers ,  Derchang Kau ,  Matthew Goldman

IPC: G11C7/00 ,  G11C13/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24

CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

公开(公告)号：US09142271B1

公开(公告)日：2015-09-22

申请号：US14313695

申请日：2014-06-24

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Doyle Rivers ,  Derchang Kau ,  Matthew Goldman

IPC: G11C7/00 ,  G11C7/12

CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

Abstract translation: 本公开涉及交叉点存储器中的参考和感测架构。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括被配置为选择与目标存储器单元相关联的全局WL（GWL）和本地WL（LWL）的字线（WL）开关电路; 配置为选择与目标存储器单元相关联的全局BL（GBL）和本地BL（LBL）的位线（BL）开关电路; 以及感测电路，包括第一感测电路电容和第二感测电路电容，所述感测电路经配置以将所选择的GWL，LWL和第一感测电路电容预充电至WL偏置电压WLVDM，产生利用电荷的参考电压（VREF） 在所选择的GWL上并对第一感测电路电容进行充电，并且至少部分地基于VREF和检测到的存储器单元电压VLWL来确定目标存储器单元的状态。