公开(公告)号：US20180096955A1

公开(公告)日：2018-04-05

申请号：US15283327

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Minsoo Lee ,  Gordon A. Haller ,  Philip J. Ireland

IPC: H01L23/58 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/3205

CPC classification number: H01L23/585 ,  H01L21/3065 ,  H01L21/32051 ,  H01L23/53271 ,  H01L23/562 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3512

Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.

公开(公告)号：US20150371925A1

公开(公告)日：2015-12-24

申请号：US14310391

申请日：2014-06-20

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Roger Lindsay ,  Minsoo Lee

IPC: H01L23/48 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Technologies for routing access lines in non-volatile memory are described. In some embodiments the technologies include forming one or more through array vias in a portion of a memory array in a non-volatile memory, such as in an array region or peripheral region, one or more access lines may be routed through the through array via, instead of within a region above or below an array or peripheral region of the memory array. This can enable alternative routing configurations, and may enable additional access lines to be routed without increasing or substantially increasing the block height of the non-volatile memory. Non-volatile memory employing such technologies is also described.

Abstract translation: 描述了用于在非易失性存储器中路由接入线路的技术。 在一些实施例中，技术包括在诸如阵列区域或外围区域的非易失性存储器中的存储器阵列的一部分中形成一个或多个贯穿阵列通孔，一个或多个访问线路可以经过穿通阵列经由 而不是在存储器阵列的阵列或外围区域的上方或下方的区域内。 这可以实现替代的路由配置，并且可以使附加的接入线路可以不增加或显着增加非易失性存储器的块高度。 还描述了采用这种技术的非易失性存储器。

公开(公告)号：US20160307914A1

公开(公告)日：2016-10-20

申请号：US15133214

申请日：2016-04-19

Applicant: Intel Corporation

Inventor： Jie Jason Sun ,  Brian Cleereman ,  Minsoo Lee

IPC: H01L27/115 ,  H01L21/822 ,  G11C16/04 ,  H01L21/28

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/0483 ,  G11C2213/71 ,  H01L21/28282 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

Abstract: An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.

Abstract translation: 集成电路可以包括半导体材料的柱，具有形成在半导体材料的柱中的沟道的场效应晶体管，以及垂直于场效应晶体管的顶部堆叠的两个或更多个存储单元，并且具有 形成在材料的柱状半导体中。

公开(公告)号：US11018097B2

公开(公告)日：2021-05-25

申请号：US16707188

申请日：2019-12-09

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Minsoo Lee ,  Gordon A. Haller ,  Philip J. Ireland

IPC: H01L23/58 ,  H01L23/532 ,  H01L21/3065 ,  H01L21/3205 ,  H01L23/00

Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.

公开(公告)号：US10229928B2

公开(公告)日：2019-03-12

申请号：US15133214

申请日：2016-04-19

Applicant: Intel Corporation

Inventor： Jie Jason Sun ,  Brian Cleereman ,  Minsoo Lee

IPC: H01L27/115 ,  H01L21/822 ,  H01L21/28 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/788 ,  H01L29/792

Abstract: An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.