公开(公告)号：US20220283951A1

公开(公告)日：2022-09-08

申请号：US17751557

申请日：2022-05-23

Applicant: Intel Corporation

Inventor： Neha PATHAPATI ,  Lidia WARNES ,  Durgesh SRIVASTAVA ,  Francois DUGAST ,  Navneet SINGH ,  Rasika SUBRAMANIAN ,  Sidharth N. KASHYAP

IPC: G06F12/0882 ,  G06F9/50 ,  G06N3/04 ,  G06K9/62

Abstract: A method is described. The method includes determining that a memory page is in one of an active state and an idle state from meta data that is maintained for the memory page. The method includes recording a past history of active/idle state determinations that were previously made for the memory page. The method includes training a neural network on the past history of the memory page. The method includes using the neural network to predict one of a future active state and future idle state for the memory page. The method includes determining a location for the memory page based on the past history of the memory page and the predicted future state of the memory page, the location being one of a faster memory and a slower memory. The method includes moving the memory page to the location from the other one of the faster memory and the slower memory.

公开(公告)号：US20240063203A1

公开(公告)日：2024-02-22

申请号：US17889962

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Navneet SINGH ,  Sushil PADMANABHAN ,  Samarth ALVA

IPC: H01L25/18 ,  H01L23/15 ,  H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/481 ,  H01L23/5384 ,  H01L21/486 ,  H01L21/4857 ,  H01L25/50 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass, and buildup layers over the first substrate. In an embodiment, a first die is over the buildup layers, a second die is over the buildup layers and adjacent to the first die, and where conductive routing in the buildup layers electrically couples the first die to the second die.

公开(公告)号：US20220200127A1

公开(公告)日：2022-06-23

申请号：US17448726

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Jayprakash THAKUR ,  Navneet SINGH ,  Aiswarya PIOUS

IPC: H01Q1/22 ,  H01Q25/04 ,  G06F1/16

Abstract: A circuit assembly for installation in a laptop lid is disclosed. The assembly includes a plurality of connectors for wired communication with a base of a laptop, and an Rf connector for wired Rf communication with the base.

公开(公告)号：US20250123749A1

公开(公告)日：2025-04-17

申请号：US19000448

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Navneet SINGH ,  Hugh WILKINSON ,  Sushant KUMAR

IPC: G06F3/06

Abstract: Examples described herein relate to hot page detection. Some examples include circuitry to provide a number of pages with access counts within a bucket of a histogram, wherein the bucket of the histogram is associated with a configured access count range; based on a distribution of access counts in the histogram being a first level, reduce the configured access count ranges of the different buckets of the histogram; determine a second level indicative of page access counts; and migrate data of pages from a far memory to a near memory based on the second level.

公开(公告)号：US20230251629A1

公开(公告)日：2023-08-10

申请号：US17667551

申请日：2022-02-09

Applicant: Intel Corporation

Inventor： Navneet SINGH ,  Samarth ALVA ,  Amarjeet KUMAR ,  Gaurav HADA

IPC: G05B19/4155

CPC classification number: G05B19/4155 ,  G05B2219/40269 ,  G05B2219/45031

Abstract: An apparatus includes a memory interposer including a socket including an inner surface, one or more memories disposed on the inner surface, a bottom surface opposite to the inner surface, and pogo pins disposed on the bottom surface and respectively corresponding to the one or more memories, the pogo pins being configured to connect the one or more memories to a printed circuit board (PCB) including a semiconductor die. The apparatus further includes an intermediate thermal head attached to the memory interposer. The memory interposer is movable with respect to the intermediate thermal head.