公开(公告)号：US20150130534A1

公开(公告)日：2015-05-14

申请号：US14599245

申请日：2015-01-16

Applicant: Intel Corporation

Inventor： Guido Droege ,  Niklas Linkewitsch ,  Andre Schaefer

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/642 ,  H01L2223/6622 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

Abstract translation: 一些实施例为3D堆叠模块提供电容AC耦合层间通信。

公开(公告)号：US09645938B2

公开(公告)日：2017-05-09

申请号：US14127483

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Tim Kranich ,  Matthias Gries ,  Niklas Linkewitsch

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0846 ,  G06F9/44 ,  G06F12/0877 ,  G06F12/0893 ,  G06F12/1045 ,  G06F12/12 ,  G06F12/0802 ,  G06F12/126

CPC classification number: G06F12/0891 ,  G06F9/4406 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0848 ,  G06F12/0877 ,  G06F12/0893 ,  G06F12/1054 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/60 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7211 ,  Y02D10/13

Abstract: In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory. It is believed that various combinations of these operations may provide improved operation of a memory. Other aspects are described herein.

公开(公告)号：US09263422B2

公开(公告)日：2016-02-16

申请号：US14599245

申请日：2015-01-16

Applicant: Intel Corporation

Inventor： Guido Droege ,  Niklas Linkewitsch ,  Andre Schaefer

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/64 ,  H01L23/522 ,  H01L23/48 ,  G11C5/06 ,  G11C7/10 ,  G11C5/04

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/642 ,  H01L2223/6622 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.