公开(公告)号：US20240329129A1

公开(公告)日：2024-10-03

申请号：US18537076

申请日：2023-12-12

Applicant: Intel Corporation

Inventor： Sridhar Muthrasanallur ,  Debendra Das Sharma ,  Swadesh Choudhary ,  Gerald Pasdast ,  Peter Onufryk

IPC: G01R31/317 ,  G06F11/27 ,  G06F13/42

CPC classification number: G01R31/31705 ,  G06F11/27 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.

公开(公告)号：US20240111701A1

公开(公告)日：2024-04-04

申请号：US18539063

申请日：2023-12-13

Applicant: Intel Corporation

Inventor： Aruni P. Nelson ,  Enrico David Carrieri ,  Rolf Kuehnis ,  Peter Onufryk ,  Sridhar Muthrasanallur

IPC: G06F13/40 ,  G06F13/22 ,  G06F13/42

CPC classification number: G06F13/4031 ,  G06F13/225 ,  G06F13/4221

Abstract: Embodiments herein relate to a universal component interconnect express (UCIe) link that includes a mainband and a sideband. One or more pieces of logic may identify a data that is to be transmitted on the sideband. The logic may then identify, based on factors such as a characteristic of the data or a characteristic of the link, whether to transmit the data on the mainband. Other embodiments may be described and/or claimed.

公开(公告)号：US20240311330A1

公开(公告)日：2024-09-19

申请号：US18399463

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Narasimha Lanka ,  Peter Onufryk ,  Swadesh Choudhary ,  Gerald Pasdast ,  Zuoguo Wu ,  Dimitrios Ziakas ,  Sridhar Muthrasanallur

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4295 ,  G06F13/1689 ,  G06F2213/0038 ,  G06F2213/0064

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.