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公开(公告)号：US20160232968A1
公开(公告)日：2016-08-11
申请号：US15025229
申请日：2013-12-05
Applicant: INTEL CORPORATION
Inventor： Nathaniel J. AUGUST , Pulkit JAIN , Stefan RUSU , Fatih HAMZAOGLU , Rangharajan VENKATESAN , Muhammad KHELLAH , Charles AUGUSTINE , Carlos TOKUNAGA , James W. TSCHANZ , Yih WANG
CPC classification number: G11C13/0061 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C13/0011 , G11C13/0014 , G11C14/0081 , G11C14/009
Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.
Abstract translation: 描述了一种包括使用电阻性存储器保持的存储单元的装置。 该装置包括：存储元件，包括交叉耦合到第二反相器件的第一反相器件; 具有至少一个电阻性存储器元件的恢复电路，所述恢复电路耦合到所述第一反相器件的输出; 耦合到所述第一反相装置的输出的第三反相装置; 耦合到第三反相装置的输出的第四反相装置; 以及具有至少一个电阻性存储器元件的保存电路，所述保存电路耦合到所述第三反相器件的输出端。
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公开(公告)号：US20200303381A1
公开(公告)日：2020-09-24
申请号：US16357221
申请日：2019-03-18
Applicant: Intel Corporation
Inventor： Elijah KARPOV , Brian DOYLE , Abhishek SHARMA , Prashant MAJHI , Pulkit JAIN
Abstract: Embodiments herein describe techniques for a semiconductor device including a SRAM device having multiple SRAM memory cells, and a capacitor coupled to the SRAM device. The capacitor includes a first plate, a second plate, and a capacitor dielectric layer between the first plate and the second plate. The capacitor is to supply power to the multiple SRAM memory cells of the SRAM device in parallel for a period of time. Other embodiments may be described and/or claimed.
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