公开(公告)号：US20190096482A1

公开(公告)日：2019-03-28

申请号：US16140441

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Raymond W. ZENG ,  Mase J. TAUB ,  Kiran PANGAL ,  Sandeep K. GULIANI

IPC: G11C13/00 ,  G11C16/34 ,  G11C16/08 ,  G11C8/06

CPC classification number: G11C13/0028 ,  G11C8/06 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/3418 ,  G11C2013/0052 ,  G11C2013/0092

Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

公开(公告)号：US20220415425A1

公开(公告)日：2022-12-29

申请号：US17358421

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Hemant P. RAO ,  Raymond W. ZENG ,  Prashant S. DAMLE ,  Zion S. KWOK ,  Kiran PANGAL ,  Mase J. TAUB

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/50 ,  G11C7/06

Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.