公开(公告)号：US20170077235A1

公开(公告)日：2017-03-16

申请号：US15123242

申请日：2014-06-13

Applicant: Intel Corporation

Inventor： Roman CAUDILLO ,  Uygar AVCI

IPC: H01L29/16 ,  H01L29/51 ,  H01L21/02 ,  H01L27/088 ,  H01L29/786 ,  H01L21/04 ,  H01L29/49 ,  H01L23/532

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y30/00 ,  H01L21/02115 ,  H01L21/02227 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/0405 ,  H01L21/044 ,  H01L23/29 ,  H01L23/53276 ,  H01L23/5329 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66984 ,  H01L29/7391 ,  H01L29/778 ,  H01L29/78684 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe multi-layer graphene assemblies including a layer of fluorinated graphene, dies and systems containing such structures, as well as methods of fabrication. The fluorinated graphene provides an insulating interface to other graphene layers while maintaining the desirable characteristics of the nonfluorinated graphene layers. The assemblies provide new options for utilizing graphene in integrated circuit devices and interfacing graphene with other materials. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了多层石墨烯组件，其包括氟化石墨烯层，模具和包含这种结构的系统，以及制造方法。 氟化石墨烯提供与其它石墨烯层的绝缘界面，同时保持非氟化石墨烯层的期望特性。 这些组件提供了在集成电路器件中利用石墨烯和将石墨烯与其他材料接合的新选择。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20210305358A1

公开(公告)日：2021-09-30

申请号：US16828497

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Manish CHANDHOK ,  Abhishek A. SHARMA ,  Roman CAUDILLO ,  Scott B. CLENDENNING ,  Cheyun LIN

IPC: H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20250120100A1

公开(公告)日：2025-04-10

申请号：US18402595

申请日：2024-01-02

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Manish CHANDHOK ,  Abhishek A. SHARMA ,  Roman CAUDILLO ,  Scott B. CLENDENNING ,  Cheyun LIN

IPC: H10B12/00

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20220140069A1

公开(公告)日：2022-05-05

申请号：US17578839

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Manish CHANDHOK ,  Abhishek A. SHARMA ,  Roman CAUDILLO ,  Scott B. CLENDENNING ,  Cheyun LIN

IPC: H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20220140068A1

公开(公告)日：2022-05-05

申请号：US17578043

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Manish CHANDHOK ,  Abhishek A. SHARMA ,  Roman CAUDILLO ,  Scott B. CLENDENNING ,  Cheyun LIN

IPC: H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.