公开(公告)号：US11417614B2

公开(公告)日：2022-08-16

申请号：US15938114

申请日：2018-03-28

申请人： Intel Corporation

发明人： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

摘要： Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US11735537B2

公开(公告)日：2023-08-22

申请号：US17852003

申请日：2022-06-28

申请人： Intel Corporation

发明人： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/645 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225

摘要： Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US10373951B1

公开(公告)日：2019-08-06

申请号：US16017247

申请日：2018-06-25

申请人： Intel Corporation

发明人： Cheng Xu ,  Rahul Jain ,  Seo Young Kim ,  Kyu Oh Lee ,  Ji Yong Park ,  Sai Vadlamani ,  Junnan Zhao

IPC分类号： H01L27/07 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02

摘要： Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

公开(公告)号：US10971492B2

公开(公告)日：2021-04-06

申请号：US16855376

申请日：2020-04-22

申请人： Intel Corporation

发明人： Cheng Xu ,  Rahul Jain ,  Seo Young Kim ,  Kyu Oh Lee ,  Ji Yong Park ,  Sai Vadlamani ,  Junnan Zhao

IPC分类号： H01L27/07 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02

摘要： Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

公开(公告)号：US20190393217A1

公开(公告)日：2019-12-26

申请号：US16402588

申请日：2019-05-03

申请人： Intel Corporation

发明人： Cheng Xu ,  Rahul Jain ,  Seo Young Kim ,  Kyu Oh Lee ,  Ji Yong Park ,  Sai Vadlamani ,  Junnan Zhao

IPC分类号： H01L27/07 ,  H01L49/02 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00

摘要： Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

公开(公告)号：US20190304661A1

公开(公告)日：2019-10-03

申请号：US15938119

申请日：2018-03-28

申请人： Intel Corporation

发明人： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC分类号： H01F27/28 ,  H01F27/24 ,  H01F27/02

摘要： Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US11355459B2

公开(公告)日：2022-06-07

申请号：US15982652

申请日：2018-05-17

申请人： Intel Corporation

发明人： Kyu-Oh Lee ,  Sai Vadlamani ,  Rahul Jain ,  Junnan Zhao ,  Ji Yong Park ,  Cheng Xu ,  Seo Young Kim

IPC分类号： H01L23/60 ,  H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F1/12 ,  H01F41/14

摘要： Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.

公开(公告)号：US11901115B2

公开(公告)日：2024-02-13

申请号：US17873509

申请日：2022-07-26

申请人： Intel Corporation

发明人： Kyu-Oh Lee ,  Rahul Jain ,  Sai Vadlamani ,  Cheng Xu ,  Ji Yong Park ,  Junnan Zhao ,  Seo Young Kim

IPC分类号： H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28 ,  H01L21/683 ,  H01L23/00

CPC分类号： H01F27/327 ,  H01F27/2804 ,  H01F41/043 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49838 ,  H01F2027/2809 ,  H01L21/6835 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/16267 ,  H01L2924/19042 ,  H01L2924/19102

摘要： Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

公开(公告)号：US11450471B2

公开(公告)日：2022-09-20

申请号：US15938119

申请日：2018-03-28

申请人： Intel Corporation

发明人： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC分类号： H01F27/24 ,  H01F27/28 ,  H01F27/02

摘要： Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US11443892B2

公开(公告)日：2022-09-13

申请号：US16020035

申请日：2018-06-27

申请人： Intel Corporation

发明人： Kyu-Oh Lee ,  Rahul Jain ,  Sai Vadlamani ,  Cheng Xu ,  Ji Yong Park ,  Junnan Zhao ,  Seo Young Kim

IPC分类号： H01L27/32 ,  H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28 ,  H01L21/683 ,  H01L23/00

摘要： Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.