公开(公告)号：US12046560B2

公开(公告)日：2024-07-23

申请号：US17555222

申请日：2021-12-17

申请人： Intel Corporation

发明人： Robert Alan May ,  Islam A. Salama ,  Sri Ranga Sai Boyapati ,  Sheng Li ,  Kristof Darmawikarta ,  Robert L. Sankman ,  Amruthavalli Pallavi Alur

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC分类号： H01L23/5389 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/112 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/22 ,  H01L2224/224 ,  H01L2224/24226 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2924/15311

摘要： A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US20240332203A1

公开(公告)日：2024-10-03

申请号：US18740068

申请日：2024-06-11

申请人： Intel Corporation

发明人： Robert Alan MAY ,  Islam A. SALAMA ,  Sri Ranga Sai BOYAPATI ,  Sheng LI ,  Kristof DARMAWIKARTA ,  Robert L. SANKMAN ,  Amruthavalli Pallavi ALUR

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC分类号： H01L23/5389 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/112 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/22 ,  H01L2224/224 ,  H01L2224/24226 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2924/15311

摘要： A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US20150064844A1

公开(公告)日：2015-03-05

申请号：US14543557

申请日：2014-11-17

申请人： Infineon Technologies AG

发明人： Joachim Mahler ,  Thomas Bemmerl ,  Anton Prueckl

IPC分类号： H01L21/768 ,  H01L25/00

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/224 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24155 ,  H01L2224/24175 ,  H01L2224/244 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/35 ,  H01L2224/352 ,  H01L2224/3701 ,  H01L2224/37113 ,  H01L2224/37118 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/40095 ,  H01L2224/40155 ,  H01L2224/40175 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/41171 ,  H01L2224/48155 ,  H01L2224/48175 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82104 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84447 ,  H01L2224/92244 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/07811 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01023 ,  H01L2224/45099

摘要： An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.

摘要翻译： 电子设备包括与第一芯片载体隔离的第一芯片载体和第二芯片载体。 第一功率半导体芯片安装在电连接到第一芯片载体上。 第二功率半导体芯片安装在第二芯片载体上并电连接到第二芯片载体。 电绝缘材料被配置为至少部分地围绕第一功率半导体芯片和第二功率半导体芯片。 电互连被配置为将第一功率半导体芯片电连接到第二功率半导体芯片，其中电互连具有接触夹和电沉积导体中的至少一个。

公开(公告)号：US08916968B2

公开(公告)日：2014-12-23

申请号：US13431125

申请日：2012-03-27

申请人： Joachim Mahler ,  Thomas Bemmerl ,  Anton Prueckl

发明人： Joachim Mahler ,  Thomas Bemmerl ,  Anton Prueckl

IPC分类号： H01L23/34

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/224 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24155 ,  H01L2224/24175 ,  H01L2224/244 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/35 ,  H01L2224/352 ,  H01L2224/3701 ,  H01L2224/37113 ,  H01L2224/37118 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/40095 ,  H01L2224/40155 ,  H01L2224/40175 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/41171 ,  H01L2224/48155 ,  H01L2224/48175 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82104 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84447 ,  H01L2224/92244 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/07811 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01023 ,  H01L2224/45099

摘要： An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.

摘要翻译： 电子设备包括与第一芯片载体隔离的第一芯片载体和第二芯片载体。 第一功率半导体芯片安装在电连接到第一芯片载体上。 第二功率半导体芯片安装在第二芯片载体上并电连接到第二芯片载体。 电绝缘材料被配置为至少部分地围绕第一功率半导体芯片和第二功率半导体芯片。 电互连被配置为将第一功率半导体芯片电连接到第二功率半导体芯片，其中电互连具有接触夹和电沉积导体中的至少一个。

公开(公告)号：US12062621B2

公开(公告)日：2024-08-13

申请号：US17849138

申请日：2022-06-24

申请人： Samsung Electronics Co., Ltd.

发明人： Jongyoun Kim

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2221/68372 ,  H01L2224/2205 ,  H01L2224/224 ,  H01L2224/95001

摘要： A semiconductor package includes a redistribution layer, a semiconductor chip on the redistribution layer, and a molding layer covering a sidewall of the semiconductor chip and a top surface and a sidewall of the redistribution layer. The sidewall of the redistribution layer is inclined with respect to a bottom surface of the redistribution layer, and a sidewall of the molding layer is spaced apart from the sidewall of the redistribution layer.

公开(公告)号：US20240072032A1

公开(公告)日：2024-02-29

申请号：US17894043

申请日：2022-08-23

申请人： QUALCOMM Incorporated

发明人： Yanmei SONG ,  William STONE ,  Jianwen XU ,  Senthil SIVASWAMY ,  John HOLMES ,  Ryan LANE

IPC分类号： H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/016 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/224 ,  H01L2224/24155 ,  H01L2224/73209 ,  H01L2224/81815 ,  H01L2224/821 ,  H01L2224/92124 ,  H01L2225/06513 ,  H01L2225/06524

摘要： A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion. The first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects. The first chiplet may include an active chiplet. The first chiplet may include a passive chiplet.

公开(公告)号：US11688726B2

公开(公告)日：2023-06-27

申请号：US17189955

申请日：2021-03-02

申请人： Kioxia Corporation

发明人： Yasunori Iwashita ,  Shinya Arai ,  Keisuke Nakatsuka ,  Takahiro Tomimatsu ,  Ryo Tanaka

IPC分类号： H01L25/18 ,  H01L23/00

CPC分类号： H01L25/18 ,  H01L24/06 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/06151 ,  H01L2224/221 ,  H01L2224/224 ,  H01L2224/8234 ,  H01L2924/1431 ,  H01L2924/1438

摘要： According to one embodiment, a semiconductor device includes a first chip, and a second chip bonded to the first chip. The first chip includes: a substrate; a transistor provided on the substrate; a plurality of first wirings provided above the transistor; and a plurality of first pads provided above the first wirings. The second chip includes: a plurality of second pads coupled to the plurality of first pads, respectively; a plurality of second wirings provided above the second pads; and a memory cell array provided above the second wirings. The first wiring, the first pad, the second pad, and the second wiring are coupled to one another in series to form a first pattern.

公开(公告)号：US20120320549A1

公开(公告)日：2012-12-20

申请号：US13515012

申请日：2010-12-17

申请人： Thomas Gottwald ,  Alexander Neumann

发明人： Thomas Gottwald ,  Alexander Neumann

IPC分类号： H05K7/00 ,  H05K3/46 ,  H01L23/48

CPC分类号： H05K1/186 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/224 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/9202 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H05K1/189 ,  H05K3/205 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/462 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/10977 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83851

摘要： The present invention relates to a method for producing a conductor structural element, comprising providing a rigid substrate, electrodepositing a copper coating on the rigid substrate, applying a conductor pattern structure to the copper coating, then possibly mounting components, laminating the substrate with at least one electrically insulating layer, detaching the rigid substrate, at least partially removing the remaining copper coating of the rigid substrate in such a way that the conductor pattern structure is exposed.

摘要翻译： 导体结构元件的制造方法技术领域本发明涉及一种导体结构元件的制造方法，其特征在于，提供刚性基板，在所述刚性基板上电沉积铜涂层，将铜导体图案结构施加到所述铜涂层上，然后可能安装部件，至少层叠所述基板 一个电绝缘层，分离刚性基板，至少部分地去除刚性基板的剩余的铜涂层，使得暴露导体图案结构。

公开(公告)号：US11894311B2

公开(公告)日：2024-02-06

申请号：US17716955

申请日：2022-04-08

申请人： Intel Corporation

发明人： Robert Alan May ,  Islam A. Salama ,  Sri Ranga Sai Boyapati ,  Sheng Li ,  Kristof Darmawikarta ,  Robert L. Sankman ,  Amruthavalli Pallavi Alur

IPC分类号： H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC分类号： H01L23/5389 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/112 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/22 ,  H01L2224/224 ,  H01L2224/24226 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2924/15311

摘要： A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US20230290758A1

公开(公告)日：2023-09-14

申请号：US17741003

申请日：2022-05-10

申请人： Century Technology (Shenzhen) Corporation Limited

发明人： KUANG-HUA LIU

IPC分类号： H01L25/075 ,  H01L33/62 ,  H01L23/00

CPC分类号： H01L25/0753 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L33/62 ,  H01L2224/19 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/224 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2933/0066

摘要： A light-emitting assembly with higher connection tolerances in manufacture includes a substrate, a light-emitting diode on the substrate, a transparent electrode, and a wire connected to the transparent electrode. The substrate includes a driving circuit connected to the light-emitting diode. The light-emitting diode includes a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode, the first electrode receiving the first driving signal. transparent electrode is connected to the second electrode. An orthographic projection area of the transparent electrode on the substrate is larger than an orthographic projection area of the second electrode on the substrate allowing less criticality in the alignment of signal wires for receiving the second driving signal. The light-emitting diode is configured to emit source light according to the first driving signal and the second driving signal.