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公开(公告)号：US20200286201A1
公开(公告)日：2020-09-10
申请号：US16297129
申请日：2019-03-08
Applicant: Intel Corporation
Inventor： James Valerio , Vasanth Ranganathan , Joydeep Ray , Abhishek R. Appu , Ben J. Ashbaugh , Brandon Fliflet , Jeffery S. Boles , Srinivasan Embar Raghukrishnan , Rahul Kulkarni
Abstract: Embodiments described herein provide an apparatus comprising a processor to configure a plurality of contexts of a command engine to execute a graphics workload comprising a plurality of walkers, allocate, from a pool of execution units of a graphics processor, a subset of execution units to each walker in the plurality of walkers based at least in part on the predetermined number of walkers configured for the context, for each context in the plurality of contexts, dispatch one or more walkers of the plurality of walkers to the execution units, and upon dispatch of the one or more walkers of the plurality of walkers, write an opcode to a computer-readable memory indicating that the dispatch of the walker is complete, wherein the opcode comprises dependency data for the one or more walkers of the plurality of walkers. Other embodiments may be described and claimed.
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公开(公告)号：US11729416B2
公开(公告)日：2023-08-15
申请号：US16651641
申请日：2017-12-29
Applicant: INTEL CORPORATION
Inventor： Srinivasan Embar Raghukrishnan , James M. Holland , Sang-Hee Lee , Atthar H. Mohammed , Dmitry E. Ryzhov , Jason Tanner , Lidong Xu , Wenhao Zhang
IPC: H04N19/577 , H04N19/513 , H04N19/567 , H04N19/96
CPC classification number: H04N19/577 , H04N19/521 , H04N19/567 , H04N19/96
Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.
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公开(公告)号：US20190222858A1
公开(公告)日：2019-07-18
申请号：US16365546
申请日：2019-03-26
Applicant: Intel Corporation
Inventor： Srinivasan Embar Raghukrishnan , Jason Tanner
IPC: H04N19/517 , H04N19/105 , H04N19/137 , H04N19/124 , H04N19/96 , H04N19/176
CPC classification number: H04N19/517 , H04N19/105 , H04N19/124 , H04N19/137 , H04N19/176 , H04N19/96
Abstract: Techniques related to coding video using out of loop inter motion estimation are discussed. Such techniques include performing simultaneous motion estimation for multiple blocks using merge candidates such that at least one of the blocks has non-final merge candidates, finalizing the merge candidates for the at least one block, and resolving reference to any non-final merge candidates that became invalid in the finalized merge candidates for final motion estimation.
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公开(公告)号：US11924435B2
公开(公告)日：2024-03-05
申请号：US16875756
申请日：2020-05-15
Applicant: INTEL CORPORATION
Inventor： Srinivasan Embar Raghukrishnan , Jason Tanner , Naiqian Lu
IPC: H04N19/139 , H04N19/103 , H04N19/119 , H04N19/184 , H04N19/436
CPC classification number: H04N19/139 , H04N19/103 , H04N19/119 , H04N19/184 , H04N19/436
Abstract: Techniques related to parallel partitioning and coding mode selection for improved video coding throughput are discussed. Such techniques include performing parallel partitioning and coding mode selection for a lower-right coding unit of a first largest coding unit and an upper-left coding unit of a second largest coding unit to the right of the first largest coding unit and, immediately subsequent thereto, performing parallel partitioning and coding mode selection for a lower-left coding unit and an upper-right coding unit of the second largest coding unit.
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公开(公告)号：US10547839B2
公开(公告)日：2020-01-28
申请号：US15651620
申请日：2017-07-17
Applicant: Intel Corporation
Inventor： Fangwen Fu , Srinivasan Embar Raghukrishnan , Atthar H. Mohammed
IPC: H04N19/147 , H04N19/124 , H04N19/52 , H04N19/176 , G06F17/11 , H04N19/103
Abstract: Systems, apparatus and methods are described including operations for video coding rate control including Rate Distortion Optimized Quantization on a block-by-block basis.
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Patent Agency Ranking
公开(公告)号：US20190200039A1
公开(公告)日：2019-06-27
申请号：US16292808
申请日：2019-03-05
Applicant: Intel Corporation
Inventor： Jason Tanner , Srinivasan Embar Raghukrishnan , James Holland
IPC: H04N19/567 , H04N19/159 , H04N19/105 , H04N19/46 , H04N19/176
CPC classification number: H04N19/567 , H04N19/105 , H04N19/159 , H04N19/176 , H04N19/46
Abstract: An embodiment of a motion estimator apparatus may include technology to receive a compound message, and perform rate distortion estimation and check refinement for two or more coding unit descriptions for a source block based on the received compound message. Other embodiments are disclosed and claimed.
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公开(公告)号：US10291925B2
公开(公告)日：2019-05-14
申请号：US15663134
申请日：2017-07-28
Applicant: Intel Corporation
Inventor： James M. Holland , Srinivasan Embar Raghukrishnan , Lidong Xu , Fangwen Fu , Dmitry E. Ryzhov , Satya N. Yedidi
IPC: H04N7/12 , H04N11/02 , H04N11/04 , H04N19/43 , H04N19/53 , H04N19/567 , H04N19/115 , H04N19/61 , H04N19/126 , H04N19/96 , H04N19/192 , H04N19/557 , H04N19/625
Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.
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公开(公告)号：US11025913B2
公开(公告)日：2021-06-01
申请号：US16400882
申请日：2019-05-01
Applicant: INTEL CORPORATION
Inventor： James M. Holland , Srinivasan Embar Raghukrishnan , Dmitry E. Ryzhov , Lidong Xu , Satya N. Yedidi , Wenhao Zhang
IPC: H04N19/176 , H04N19/147 , H04N19/567 , H04N19/124 , H04N19/105
Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.
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公开(公告)号：US10944987B2
公开(公告)日：2021-03-09
申请号：US16292808
申请日：2019-03-05
Applicant: Intel Corporation
Inventor： Jason Tanner , Srinivasan Embar Raghukrishnan , James Holland
IPC: H04N19/567 , H04N19/159 , H04N19/176 , H04N19/46 , H04N19/105 , H04N19/107 , H04N19/436 , H04N19/147
Abstract: An embodiment of a motion estimator apparatus may include technology to receive a compound message, and perform rate distortion estimation and check refinement for two or more coding unit descriptions for a source block based on the received compound message. Other embodiments are disclosed and claimed.
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公开(公告)号：US20200280722A1
公开(公告)日：2020-09-03
申请号：US16875756
申请日：2020-05-15
Applicant: INTEL CORPORATION
Inventor： Srinivasan Embar Raghukrishnan , Jason Tanner , Naiqian Lu
IPC: H04N19/139 , H04N19/103 , H04N19/119 , H04N19/184 , H04N19/436
Abstract: Techniques related to parallel partitioning and coding mode selection for improved video coding throughput are discussed. Such techniques include performing parallel partitioning and coding mode selection for a lower-right coding unit of a first largest coding unit and an upper-left coding unit of a second largest coding unit to the right of the first largest coding unit and, immediately subsequent thereto, performing parallel partitioning and coding mode selection for a lower-left coding unit and an upper-right coding unit of the second largest coding unit.
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