公开(公告)号：US20170214938A1

公开(公告)日：2017-07-27

申请号：US15002697

申请日：2016-01-21

申请人： INTEL CORPORATION

发明人： Ximin Zhang ,  Sang-Hee Lee ,  Dmitry E. Ryzhov

IPC分类号： H04N19/58 ,  H04N19/146 ,  H04N19/177 ,  H04N19/126 ,  H04N19/70 ,  H04N19/593

CPC分类号： H04N19/58 ,  H04N19/124 ,  H04N19/126 ,  H04N19/142 ,  H04N19/146 ,  H04N19/159 ,  H04N19/172 ,  H04N19/177 ,  H04N19/593 ,  H04N19/70

摘要： Techniques related to long term reference picture video coding are discussed. Such techniques may include determining long term reference pictures for a sequence of pictures, adjusting the quantization parameters for the long term reference pictures, and managing reference picture lists.

公开(公告)号：US11729416B2

公开(公告)日：2023-08-15

申请号：US16651641

申请日：2017-12-29

申请人： INTEL CORPORATION

发明人： Srinivasan Embar Raghukrishnan ,  James M. Holland ,  Sang-Hee Lee ,  Atthar H. Mohammed ,  Dmitry E. Ryzhov ,  Jason Tanner ,  Lidong Xu ,  Wenhao Zhang

IPC分类号： H04N19/577 ,  H04N19/513 ,  H04N19/567 ,  H04N19/96

CPC分类号： H04N19/577 ,  H04N19/521 ,  H04N19/567 ,  H04N19/96

摘要： An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.

公开(公告)号：US20160366413A1

公开(公告)日：2016-12-15

申请号：US14737790

申请日：2015-06-12

申请人： Intel Corporation

发明人： Ximin Zhang ,  Sang-Hee Lee ,  Dmitry E. Ryzhov

IPC分类号： H04N19/132 ,  H04N19/124 ,  H04N19/577 ,  H04N19/139 ,  H04N19/13 ,  H04N19/196 ,  H04N19/52 ,  H04N19/179 ,  H04N19/142 ,  H04N19/114 ,  H04N19/177

CPC分类号： H04N19/132 ,  H04N19/114 ,  H04N19/117 ,  H04N19/124 ,  H04N19/13 ,  H04N19/139 ,  H04N19/142 ,  H04N19/146 ,  H04N19/159 ,  H04N19/172 ,  H04N19/177 ,  H04N19/179 ,  H04N19/197 ,  H04N19/52 ,  H04N19/577 ,  H04N19/82

摘要： Techniques related to video coding with sample adaptive offset coding are discussed. Such techniques may include setting a sample adaptive offset coding flag for a picture of a group of pictures based at least in part on a comparison of an available coding bit limit of the picture to a first threshold and a quantization parameter of the picture to a second threshold. In some examples, such techniques may also include setting the sample adaptive offset coding flag based on a coding structure associated with coding the group of pictures.

摘要翻译： 讨论了与样本自适应偏移编码相关的视频编码技术。 这样的技术可以包括至少部分地基于图像的可用编码比特限制与第一阈值和图像的量化参数的比较来设置用于一组图像的图像的样本自适应偏移编码标志 阈。 在一些示例中，这样的技术还可以包括基于与图像组编码相关联的编码结构来设置样本自适应偏移编码标志。

公开(公告)号：US11025913B2

公开(公告)日：2021-06-01

申请号：US16400882

申请日：2019-05-01

申请人： INTEL CORPORATION

发明人： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi ,  Wenhao Zhang

IPC分类号： H04N19/176 ,  H04N19/147 ,  H04N19/567 ,  H04N19/124 ,  H04N19/105

摘要： A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.

公开(公告)号：US20190297344A1

公开(公告)日：2019-09-26

申请号：US16440159

申请日：2019-06-13

申请人： INTEL CORPORATION

发明人： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC分类号： H04N19/533 ,  H04N19/159 ,  H04N19/60 ,  H04N19/88 ,  H04N19/70 ,  H04N19/176

摘要： An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.

公开(公告)号：US20190261001A1

公开(公告)日：2019-08-22

申请号：US16400882

申请日：2019-05-01

申请人： INTEL CORPORATION

发明人： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi ,  Wenhao Zhang

IPC分类号： H04N19/147 ,  H04N19/176 ,  H04N19/105 ,  H04N19/124 ,  H04N19/567

摘要： A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.

公开(公告)号：US20190037227A1

公开(公告)日：2019-01-31

申请号：US15663134

申请日：2017-07-28

申请人： Intel Corporation

发明人： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Lidong Xu ,  Fangwen Fu ,  Dmitry E. Ryzhov ,  Satya N. Yedidi

IPC分类号： H04N19/43 ,  H04N19/53 ,  H04N19/567 ,  H04N19/115 ,  H04N19/61 ,  H04N19/126 ,  H04N19/96 ,  H04N19/192 ,  H04N19/557

摘要： An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.

公开(公告)号：US20230097092A1

公开(公告)日：2023-03-30

申请号：US17978290

申请日：2022-11-01

申请人： Intel Corporation

发明人： Shriram S. Deshpande ,  Satya N. Yedidi ,  James M. Holland ,  Dmitry E. Ryzhov ,  Jian Hu ,  Sai Agnihotri ,  Indira Munagani

IPC分类号： H04N19/124 ,  H04N19/52 ,  H04N19/184

摘要： Techniques related to video encoding include inline downscaling hardware in multi-pass encoding.

公开(公告)号：US20200314447A1

公开(公告)日：2020-10-01

申请号：US16651641

申请日：2017-12-29

申请人： INTEL CORPORATION

发明人： Srinivas Embar Raghukrishnan ,  James M. Holland ,  Sang-Hee Lee ,  Atthar H. Mohammed ,  Dmitry E. Ryzhov ,  Jason Tanner ,  Lidong Xu ,  Wenhao Zhang

IPC分类号： H04N19/577 ,  H04N19/567 ,  H04N19/513

摘要： An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.

公开(公告)号：US10291925B2

公开(公告)日：2019-05-14

申请号：US15663134

申请日：2017-07-28

申请人： Intel Corporation

发明人： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Lidong Xu ,  Fangwen Fu ,  Dmitry E. Ryzhov ,  Satya N. Yedidi

IPC分类号： H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/43 ,  H04N19/53 ,  H04N19/567 ,  H04N19/115 ,  H04N19/61 ,  H04N19/126 ,  H04N19/96 ,  H04N19/192 ,  H04N19/557 ,  H04N19/625

摘要： An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.