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9 条记录 (耗时 0.013 秒)

    Asynchronous on-die eye scope
    1.
    发明授权
    Asynchronous on-die eye scope 有权

    公开(公告)号：US09922248B2

    公开(公告)日：2018-03-20

    申请号：US14865401

    申请日：2015-09-25

    申请人： Intel Corporation

    发明人： Mingming Xu ,  Stefano Giaconi ,  Wei Wang

    IPC分类号： H04L27/14 ,  G06K9/00 ,  G01R13/02

    CPC分类号： G06K9/0053 ,  G01R13/02 ,  G06K9/00503 ,  G06K9/00557 ,  G06K9/00604

    摘要： Some embodiments include apparatuses and methods having a receiver unit included in a die and a measurement unit included in the die. The receiver unit includes a sampler to sample a first signal based on timing of a first clock signal to generate a second signal. The measurement unit is arranged to sample the first signal based on timing of a second clock signal to provide information for generation of a graph presenting an eye scan of the first signal. The second clock signal has a frequency asynchronous with a frequency of the first clock signal.

    Phase adjustment circuit for clock and data recovery circuit
    4.
    发明授权
    Phase adjustment circuit for clock and data recovery circuit 有权
    时钟和数据恢复电路的相位调整电路

    公开(公告)号：US09559878B2

    公开(公告)日：2017-01-31

    申请号：US15019835

    申请日：2016-02-09

    申请人： Intel Corporation

    发明人： Stefano Giaconi ,  Mingming Xu

    IPC分类号： H04L25/03 ,  H04L7/00 ,  H04L7/033

    CPC分类号： H04L25/03057 ,  H04L7/0041 ,  H04L7/0058 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0332 ,  H04L7/0334 ,  H04L25/03025 ,  H04L2025/03598

    摘要： Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.

    摘要翻译： 描述了时钟和数据恢复电路（CDR）的相位调整电路。 系统和装置可以包括用于接收串行数据信号的输入端，边缘数据抽头以对串行数据信号中的过渡边缘进行采样以产生数据边缘检测信号; CDR电路，包括用于接收串行数据信号的相位检测器和 数据边缘检测信号，并输出指示串行数据信号和数据边缘检测信号之间的相位差的相位超前/滞后信号，以及产生相位超前/滞后调整数据的相位调整电路。 CDR电路至少部分地基于由相位超前/滞后调整数据调整的相位超前/滞后信号来输出恢复的时钟信号。