公开(公告)号：US20170133462A1

公开(公告)日：2017-05-11

申请号：US15410649

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  B82Y10/00 ,  H01L27/12

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20200227520A1

公开(公告)日：2020-07-16

申请号：US16831692

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L29/165 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20160372597A1

公开(公告)日：2016-12-22

申请号：US15250836

申请日：2016-08-29

Applicant: Intel Corporation

Inventor： Titash RAKSHIT ,  Martin GILES ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/7845 ,  H01L21/8234 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

公开(公告)号：US20150303258A1

公开(公告)日：2015-10-22

申请号：US14789856

申请日：2015-07-01

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. Cea ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L27/12 ,  H01L29/165 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。