公开(公告)号：US20240145368A1

公开(公告)日：2024-05-02

申请号：US17975662

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Ravindra RUDRARAJU ,  Vijay KASTURI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/1432 ,  H01L2924/14361

Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a package substrate with a top substrate surface and an interposer coupled to the package substrate at the top substrate surface. The interposer may include a plurality of through interposer vias and an opening extending through the interposer. A power module may be arranged in the opening in the interposer and coupled to the package substrate at the top substrate surface. The power module may include a plurality of interconnects including a first interconnect coupled to a first voltage and a second interconnect coupled to a second voltage.

公开(公告)号：US20180005947A1

公开(公告)日：2018-01-04

申请号：US15201337

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Vijay KASTURI ,  Ana M. YEPES ,  Chung-Hao CHEN ,  Bradley A. JACKSON

IPC: H01L23/538 ,  H01L23/15 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/5387 ,  H01L2224/16225

Abstract: Techniques and mechanisms for interconnecting circuitry disposed on a transparent substrate. In an embodiment, a multilayer circuit is bonded to the transparent substrate, the multilayer circuit including conductive traces that are variously offset at different respective levels from a side of the transparent substrate. Circuit components, such as packaged or unpackaged integrated circuit devices, are coupled each to respective input and/or output (IO) contacts of the multilayer circuit, where the conductive traces and the IO contacts interconnect the circuit components with each other. In another embodiment, the multilayer circuit is a flexible circuit that is bent to interconnect circuit components which are disposed on opposite respective sides of the transparent substrate.

公开(公告)号：US20170162987A1

公开(公告)日：2017-06-08

申请号：US14962131

申请日：2015-12-08

Applicant: INTEL CORPORATION

Inventor： Vijay KASTURI

IPC: H01R24/50 ,  H05K1/02

CPC classification number: H01R24/50 ,  H01R12/526 ,  H01R12/53 ,  H05K1/0219 ,  H05K1/0298 ,  H05K1/117 ,  H05K1/14 ,  H05K3/32 ,  H05K2201/09236 ,  H05K2201/09481 ,  H05K2201/10189 ,  H05K2201/10356

Abstract: An adaptor board may include a multi-layer circuit board having at least three layers, namely a first board layer, a second board layer, and a third board layer. A first plurality of cable contacts may be provided at the first board layer, and a second plurality of cable contacts may be provided at the third board layer.