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    Low power oversampling with reduced-architecture delay locked loop
    1.
    发明授权
    Low power oversampling with reduced-architecture delay locked loop 有权
    低功耗过采样与减少架构延迟锁定环路

    公开(公告)号：US09231753B2

    公开(公告)日：2016-01-05

    申请号：US14326657

    申请日：2014-07-09

    申请人： Intel Corporation

    发明人： Wei-Lien Yang

    IPC分类号： H03L7/06 ,  H04L7/00 ,  H04L25/49 ,  H03L7/081 ,  H03L7/16

    CPC分类号： H04L7/0037 ,  H03L7/0818 ,  H03L7/16 ,  H04L25/4902

    摘要： In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

    摘要翻译： 在一个实施例中，一种装置，包括相位检测器单元，用于确定反相参考时钟信号和反馈时钟信号之间的相位差。 该装置还包括一个控制器单元，用于根据相位差产生延迟信号。 该装置还包括一组电压控制延迟线，以基于延迟信号产生相位输出，其中相位输出由该装置提供给时钟发生器单元，以产生用于由接收器进行数据恢复的过采样时钟信号。

    Low power data recovery
    2.
    发明授权
    Low power data recovery 有权
    低功耗数据恢复

    公开(公告)号：US08823432B2

    公开(公告)日：2014-09-02

    申请号：US14141589

    申请日：2013-12-27

    申请人： Intel Corporation

    发明人： Wei-Lien Yang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0807 ,  H03L7/0802 ,  H04L7/0331 ,  H04L25/4902

    摘要： In one embodiment, an apparatus may include a pulse generator to generate an oversampled clock signal. The apparatus may also include a sample and hold unit to provide at least two differential input signals based on the oversampled clock signal. The apparatus may further include a conversion unit to generate a single-ended signal based on the at least two differential input signals. The apparatus may also include a counter to determine a count of rising and falling edges of the single-ended signal based on the oversampled clock signal.

    摘要翻译： 在一个实施例中，装置可以包括用于产生过采样时钟信号的脉冲发生器。 该装置还可以包括采样和保持单元，用于基于过采样时钟信号提供至少两个差分输入信号。 该装置还可以包括转换单元，用于基于至少两个差分输入信号产生单端信号。 该装置还可以包括计数器，用于基于过采样的时钟信号来确定单端信号的上升沿和下降沿的计数。

    Data interface clock generation
    3.
    发明授权
    Data interface clock generation 有权
    数据接口时钟生成

    公开(公告)号：US08890726B2

    公开(公告)日：2014-11-18

    申请号：US14181969

    申请日：2014-02-17

    申请人： Intel Corporation

    发明人： Wei-Lien Yang

    IPC分类号： H03M9/00 ,  H03K3/017 ,  H03L7/08 ,  H04L7/033 ,  H03K23/68 ,  H04L1/00 ,  H03L7/089

    CPC分类号： H03K3/017 ,  H03K23/68 ,  H03L7/08 ,  H03L7/0891 ,  H03M9/00 ,  H04L1/0003 ,  H04L7/033

    摘要： In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data.

    摘要翻译： 在一个实施例中，装置可以包括时钟发生器以产生第一时钟信号。 该装置还可以包括基于传输时钟信号和并行输入数据产生串行数据的串行器。 该装置还可以包括基于第一时钟信号和串行数据产生至少两个差分信号的信号发生器。

    Pulse width modulation receiver circuitry
    4.
    发明授权
    Pulse width modulation receiver circuitry 有权
    脉宽调制接收机电路

    公开(公告)号：US08848850B2

    公开(公告)日：2014-09-30

    申请号：US13626460

    申请日：2012-09-25

    申请人： Intel Corporation

    发明人： Wei-Lien Yang

    IPC分类号： H04L7/02

    CPC分类号： H03K9/08

    摘要： Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data signal, where a count is started in response to the bit being subsequently shifted out of the shift circuit. Based on a value of the count, the receiver circuit generates a control signal for preparing physical layer receiver logic to transition to a burst mode of operation. In another embodiment, a receiver circuit includes a frequency divider to operate based on a data signal and a clock signal, wherein, based on operation of the frequency counter, a control signal is generated to indicate a line reset for physical layer receiver logic. The receiver circuit provides a feedback signal, based on the control signal, which is to limit activation of the frequency divider.

    摘要翻译： 评估高速I / O接收器逻辑数据的机制和技术。 在一个实施例中，接收机电路响应于数据信号的上升沿将位移位到移位电路中，其中响应于位被移出移位电路而开始计数。 基于计数值，接收器电路产生用于准备物理层接收器逻辑以转换到突发操作模式的控制信号。 在另一个实施例中，接收机电路包括一个基于数据信号和时钟信号进行操作的分频器，其中，基于频率计数器的操作，生成控制信号以指示物理层接收机逻辑的线路复位。 接收器电路基于控制信号提供反馈信号，该信号限制分频器的激活。

    Low power oversampling with delay locked loop implementation
    5.
    发明授权
    Low power oversampling with delay locked loop implementation 有权
    具有延迟锁定环路实现的低功耗过采样

    公开(公告)号：US09143314B2

    公开(公告)日：2015-09-22

    申请号：US14301745

    申请日：2014-06-11

    申请人： Intel Corporation

    发明人： Wei-Lien Yang

    IPC分类号： H04L7/033 ,  H03K7/08 ,  H03L7/081 ,  H03L7/091

    CPC分类号： H04L7/033 ,  H03L7/0812 ,  H03L7/091

    摘要： In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

    摘要翻译： 在一个实施例中，一种装置，包括用于确定参考时钟信号和反馈时钟信号之间的相位差的相位检测器单元。 该装置还包括一个控制器单元，用于根据相位差产生延迟信号。 该装置还包括一组电压控制的延迟线，以基于延迟信号产生相位输出，其中相位输出由该装置提供给时钟发生器单元，以产生用于由接收器进行数据恢复的过采样时钟信号。

    PULSE WIDTH MODULATION RECEIVER CIRCUITRY
    6.
    发明申请
    PULSE WIDTH MODULATION RECEIVER CIRCUITRY 有权
    脉冲宽度调制接收器电路

    公开(公告)号：US20140086363A1

    公开(公告)日：2014-03-27

    申请号：US13626460

    申请日：2012-09-25

    申请人： INTEL CORPORATION

    发明人： Wei-Lien Yang

    IPC分类号： H04B1/18

    CPC分类号： H03K9/08

    摘要： Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data signal, where a count is started in response to the bit being subsequently shifted out of the shift circuit. Based on a value of the count, the receiver circuit generates a control signal for preparing physical layer receiver logic to transition to a burst mode of operation. In another embodiment, a receiver circuit includes a frequency divider to operate based on a data signal and a clock signal, wherein, based on operation of the frequency counter, a control signal is generated to indicate a line reset for physical layer receiver logic. The receiver circuit provides a feedback signal, based on the control signal, which is to limit activation of the frequency divider.

    摘要翻译： 评估高速I / O接收器逻辑数据的机制和技术。 在一个实施例中，接收机电路响应于数据信号的上升沿将位移位到移位电路中，其中响应于位被移出移位电路而开始计数。 基于计数值，接收器电路产生用于准备物理层接收器逻辑以转换到突发操作模式的控制信号。 在另一个实施例中，接收机电路包括一个基于数据信号和时钟信号进行操作的分频器，其中，基于频率计数器的操作，生成控制信号以指示物理层接收机逻辑的线路复位。 接收器电路基于控制信号提供反馈信号，该信号限制分频器的激活。

    Low Power Oversampling With Reduced-Architecture Delay Locked Loop
    7.
    发明申请
    Low Power Oversampling With Reduced-Architecture Delay Locked Loop 审中-公开
    具有减少架构延迟锁定环路的低功耗过采样

    公开(公告)号：US20140369400A1

    公开(公告)日：2014-12-18

    申请号：US14326657

    申请日：2014-07-09

    申请人： Intel Corporation

    发明人： Wei-Lien Yang

    IPC分类号： H04L7/00 ,  H04L25/49

    CPC分类号： H04L7/0037 ,  H03L7/0818 ,  H03L7/16 ,  H04L25/4902

    摘要： In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

    摘要翻译： 在一个实施例中，一种装置，包括相位检测器单元，用于确定反相参考时钟信号和反馈时钟信号之间的相位差。 该装置还包括一个控制器单元，用于根据相位差产生延迟信号。 该装置还包括一组电压控制延迟线，以基于延迟信号产生相位输出，其中相位输出由该装置提供给时钟发生器单元，以产生用于由接收器进行数据恢复的过采样时钟信号。

    LOW POWER TRANSMITTER FOR GENERATING PULSE MODULATED SIGNALS
    8.
    发明申请
    LOW POWER TRANSMITTER FOR GENERATING PULSE MODULATED SIGNALS 有权
    用于产生脉冲调制信号的低功率发射器

    公开(公告)号：US20140226708A1

    公开(公告)日：2014-08-14

    申请号：US13993308

    申请日：2011-12-15

    申请人： INTEL CORPORATION

    发明人： Wei-Lien Yang

    IPC分类号： H04L25/49

    CPC分类号： H04L25/4902 ,  H03K7/08

    摘要： Described herein are an apparatus, system, and method for generating pulse modulated (PWM) signals. The apparatus (e.g., input-output transmitter) comprises: an edge detector to detect one of a rising or falling edges of a clock signal; a counter to count up or down in response to detecting one of the rising or falling edges of the clock signal, the counter to generate a select signal; and a control unit to receive a data signal for transmission to a receiver and to generate a PWM signal as output according to a value of the select signal and the data signal, wherein the receiver and the transmitter are a Mobile Industry Processor Interface (MIPI®) M-PHYSM receiver and transmitter.

    摘要翻译： 这里描述了用于产生脉冲调制（PWM）信号的装置，系统和方法。 该装置（例如，输入 - 输出发射机）包括：边缘检测器，用于检测时钟信号的上升沿或下降沿之一; 响应于检测到所述时钟信号的上升沿或下降沿之一响应于向上或向下计数的计数器，所述计数器产生选择信号; 以及控制单元，用于接收用于传输到接收机的数据信号，并根据所述选择信号和所述数据信号的值产生作为输出的PWM信号，其中所述接收机和所述发射机是移动工业处理器接口（MIPI ）M-PHYSM接收机和发射机。