GALLIUM ALLOYS AS FILLERS FOR POLYMER THERMAL INTERFACE MATERIALS

    公开(公告)号:US20220199489A1

    公开(公告)日:2022-06-23

    申请号:US17552241

    申请日:2021-12-15

    申请人: Intel Corporation

    IPC分类号: H01L23/373

    摘要: Embodiments disclosed herein include polymer thermal interface materials. In an embodiment a thermal interface material (TIM) comprises a polymer matrix and a liquid metal filler in the polymer matrix. In an embodiment, the liquid metal filler comprises a liquid core and an oxide layer around the liquid core. In an embodiment, the liquid core comprises gallium or a gallium alloy, and the oxide layer comprises a metal oxide other than gallium oxide.

    ENHANCED BASE DIE HEAT PATH USING THROUGH-SILICON VIAS

    公开(公告)号:US20230128903A1

    公开(公告)日:2023-04-27

    申请号:US18088478

    申请日:2022-12-23

    申请人: Intel Corporation

    摘要: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

    LOW FORCE LIQUID METAL INTERCONNECT SOLUTIONS

    公开(公告)号:US20210392774A1

    公开(公告)日:2021-12-16

    申请号:US16902048

    申请日:2020-06-15

    申请人: Intel Corporation

    IPC分类号: H05K7/14 H05K7/20

    摘要: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

    ENHANCED BASE DIE HEAT PATH USING THROUGH-SILICON VIAS

    公开(公告)号:US20210257277A1

    公开(公告)日:2021-08-19

    申请号:US16794789

    申请日:2020-02-19

    申请人: Intel Corporation

    摘要: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

    LOW FORCE LIQUID METAL INTERCONNECT SOLUTIONS

    公开(公告)号:US20230209759A1

    公开(公告)日:2023-06-29

    申请号:US18112953

    申请日:2023-02-22

    申请人: Intel Corporation

    IPC分类号: H05K7/14 H05K7/20 H01L23/22

    摘要: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.