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公开(公告)号:US20240282667A1
公开(公告)日:2024-08-22
申请号:US18635894
申请日:2024-04-15
申请人: Intel Corporation
发明人: Weston BERTRAND , Kyle ARRINGTON , Shankar DEVASENATHIPATHY , Aaron MCCANN , Nicholas NEAL , Zhimin WAN
IPC分类号: H01L23/433 , H01L23/367 , H01L25/065
CPC分类号: H01L23/433 , H01L23/3675 , H01L25/0657
摘要: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
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公开(公告)号:US20220199489A1
公开(公告)日:2022-06-23
申请号:US17552241
申请日:2021-12-15
申请人: Intel Corporation
IPC分类号: H01L23/373
摘要: Embodiments disclosed herein include polymer thermal interface materials. In an embodiment a thermal interface material (TIM) comprises a polymer matrix and a liquid metal filler in the polymer matrix. In an embodiment, the liquid metal filler comprises a liquid core and an oxide layer around the liquid core. In an embodiment, the liquid core comprises gallium or a gallium alloy, and the oxide layer comprises a metal oxide other than gallium oxide.
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公开(公告)号:US20230128903A1
公开(公告)日:2023-04-27
申请号:US18088478
申请日:2022-12-23
申请人: Intel Corporation
发明人: Weston BERTRAND , Kyle ARRINGTON , Shankar DEVASENATHIPATHY , Aaron MCCANN , Nicholas NEAL , Zhimin WAN
IPC分类号: H01L23/433 , H01L25/065 , H01L23/367
摘要: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
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公开(公告)号:US20210392774A1
公开(公告)日:2021-12-16
申请号:US16902048
申请日:2020-06-15
申请人: Intel Corporation
发明人: Karumbu MEYYAPPAN , Kyle ARRINGTON , David CRAIG , Pooya TADAYON
摘要: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.
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公开(公告)号:US20240332125A1
公开(公告)日:2024-10-03
申请号:US18128848
申请日:2023-03-30
申请人: Intel Corporation
发明人: Kyle ARRINGTON , Clay ARRINGTON , Bohan SHAN , Haobo CHEN , Srinivas V. PIETAMBARAM , Gang DUAN , Ziyin LIN , Hongxia FENG , Yiqun BAI , Xiaoying GUO , Dingying XU , Bai NIE
IPC分类号: H01L23/373 , H01L21/48 , H01L23/24 , H01L23/498
CPC分类号: H01L23/3737 , H01L21/4857 , H01L21/486 , H01L23/24 , H01L23/49822 , H01L23/49827
摘要: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a first layer and a second layer over the first layer. In an embodiment, the second layer comprises a dielectric material including sulfur. In an embodiment, fillers are within the second layer. In an embodiment, the fillers have a volume fraction that is less than approximately 0.2.
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公开(公告)号:US20230290661A1
公开(公告)日:2023-09-14
申请号:US17692247
申请日:2022-03-11
申请人: Intel Corporation
发明人: Kyle ARRINGTON , Kirk WHEELER , Emily SCHUBERT , Dingying XU , Bassam ZIADEH
IPC分类号: H01L21/673
CPC分类号: H01L21/67336 , H01L21/67356 , H01L21/67366 , H01L21/67369 , H01L21/67386 , H01L21/67396
摘要: The present disclosure relates to a tray assembly. The tray assembly may include a die transport tray. The die transport tray may include an inner bottom surface for accommodating a plurality of dies. The tray assembly may further include a lid. The lid may include an inner top surface, wherein the inner top surface of the lid may face the inner bottom surface of the die transport tray when the lid is assembled over the die transport tray. The lid may further include a shock absorbing material on the inner top surface for contacting the plurality of dies, if present.
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公开(公告)号:US20240071848A1
公开(公告)日:2024-02-29
申请号:US17895916
申请日:2022-08-25
申请人: Intel Corporation
发明人: Bohan SHAN , Haobo CHEN , Brandon C. MARIN , Srinivas V. PIETAMBARAM , Bai NIE , Gang DUAN , Kyle ARRINGTON , Ziyin LIN , Hongxia FENG , Yiqun BAI , Xiaoying GUO , Dingying David XU , Jeremy D. ECTON , Kristof DARMAWIKARTA , Suddhasattwa NAD
IPC分类号: H01L23/15 , H01L21/48 , H01L23/498
CPC分类号: H01L23/15 , H01L21/486 , H01L23/49816 , H01L23/49827
摘要: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.
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公开(公告)号:US20210257277A1
公开(公告)日:2021-08-19
申请号:US16794789
申请日:2020-02-19
申请人: Intel Corporation
发明人: Weston BERTRAND , Kyle ARRINGTON , Shankar DEVASENATHIPATHY , Aaron MCCANN , Nicholas NEAL , Zhimin WAN
IPC分类号: H01L23/433 , H01L23/367 , H01L25/065
摘要: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
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公开(公告)号:US20230317706A1
公开(公告)日:2023-10-05
申请号:US17710753
申请日:2022-03-31
申请人: Intel Corporation
发明人: Kyle ARRINGTON , Kuang LIU , Bohan SHAN , Hongxia FENG , Don Douglas JOSEPHSON , Stephen MOREIN , Kaladhar RADHAKRISHNAN
IPC分类号: H01L25/18 , H01L23/373 , H01L25/065 , H01L23/00 , H01L23/538 , H01L21/48
CPC分类号: H01L25/18 , H01L23/3736 , H01L25/0652 , H01L24/40 , H01L23/538 , H01L21/4871 , H01L24/37 , H01L2224/37147 , H01L24/83 , H01L2224/83385 , H01L2224/83447 , H01L24/33 , H01L2224/3303 , H01L24/06 , H01L2224/0603 , H01L2224/32258 , H01L2224/4046 , H01L24/32 , H01L2224/40499 , H01L24/16 , H01L2224/16225
摘要: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.
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公开(公告)号:US20230209759A1
公开(公告)日:2023-06-29
申请号:US18112953
申请日:2023-02-22
申请人: Intel Corporation
发明人: Karumbu MEYYAPPAN , Kyle ARRINGTON , David CRAIG , Pooya TADAYON
CPC分类号: H05K7/1481 , H05K7/20272 , H01L23/22
摘要: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.
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