公开(公告)号：US20220262431A1

公开(公告)日：2022-08-18

申请号：US17737461

申请日：2022-05-05

Applicant: Intel NDTM US LLC

Inventor： Sagar Upadhyay ,  Aliasgar S. Madraswala ,  John Egler

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: Systems, apparatuses, and methods provide for technology for distinguishing an erased state, a first pass programmed state, and a second pass programmed state of a memory page. A threshold voltage state verify sense is performed. A memory page status is determined based on the threshold voltage state verify sense. The memory page status is one of erased, programmed with first pass data, and programmed with second pass data based on the threshold voltage state verify sense. A program continuation is performed after a program interruption based on the memory page status.

公开(公告)号：US12189955B2

公开(公告)日：2025-01-07

申请号：US18089969

申请日：2022-12-28

Applicant: Intel NDTM US LLC

Inventor： Archana Tankasala ,  Sagar Upadhyay ,  Shantanu R. Rajwade ,  Aliasgar S. Madraswala

IPC: G06F3/06

Abstract: Skip program verify for dynamic start voltage (DSV) sampling reduces latency of a program operation on multi-level cell (MLC) memory having at least two pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND device. The NAND device skips program verifies corresponding to higher levels of voltage thresholds during DSV sampling. As a result, the NAND device can reduce a total program time (tPROG) to program the MLC memory, and determine the dynamic start program voltage more quickly. The NAND device can improve an effective TLC NAND tPROG by as much as 2% without impacting the placement of the first sub-block being programmed. The skipped program verifies corresponding to the higher levels of voltage thresholds are resumed as soon as DSV sampling is complete.

公开(公告)号：US12046303B2

公开(公告)日：2024-07-23

申请号：US16895890

申请日：2020-06-08

Applicant: Intel NDTM US LLC

Inventor： Pranav Chava ,  Aliasgar S. Madraswala ,  Sagar Upadhyay ,  Bhaskar Venkataramaiah

IPC: G11C16/12 ,  G11C7/22 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C7/222 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.

公开(公告)号：US20230138471A1

公开(公告)日：2023-05-04

申请号：US18089422

申请日：2022-12-27

Applicant: Intel NDTM US LLC

Inventor： Binh Ngo ,  Moonkyun Maeng ,  Navid Paydavosi ,  Sagar Upadhyay ,  Sanket Sanjay Wadyalkar ,  Soo-yong Park

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to monitor a sense voltage for an operation associated with a wordline of the NAND memory, and adjust a negative charge pump for the wordline prior to completion of the operation based on the monitored sense voltage. Other examples are disclosed and claimed.

公开(公告)号：US12230334B2

公开(公告)日：2025-02-18

申请号：US17710978

申请日：2022-03-31

Applicant: Intel NDTM US LLC

Inventor： Aliasgar S. Madraswala ,  Ali Khakifirooz ,  Bhaskar Venkataramaiah ,  Sagar Upadhyay ,  Yogesh B. Wakchaure

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

Abstract: Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller determines that the program operation can be initiated without loading all pages into the memory. In response, the NAND loads a first page and then executes portions of the program operation in parallel, at least in part, with loading subsequent pages. The NAND behavior is modified to monitor data loading completion times, to copy pages from a cache register to a data register as needed, and to resume program operation if a shutdown occurs. The portions of the program operation include a program prologue operation and a pulse verify loop for the first voltage level (L1) of the MLC memory.

公开(公告)号：US20230376215A1

公开(公告)日：2023-11-23

申请号：US18086315

申请日：2022-12-21

Applicant: Intel NDTM US LLC

Inventor： Aliasgar S Madraswala ,  Xin Sun ,  Naveen Prabhu Vittal Prabhu ,  Sagar Upadhyay

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0634

Abstract: An example of a memory device may comprise NAND media with a plurality of decks, and circuitry coupled to the NAND media to control access to a superblock of memory cells aligned along a pillar of the NAND media, wherein the superblock includes at least a first block that corresponds to memory cells aligned along the pillar in a first deck of the plurality of decks and a second block that corresponds to memory cells aligned along the pillar in a second deck of the plurality of decks, configure the NAND media in a first program mode for the first block of the superblock, and configure the NAND media in a second program mode for the second block of the superblock. Other examples are disclosed and claimed.