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1.发明授权公开(公告)号：US11139385B2
公开(公告)日：2021-10-05
申请号：US15982507
申请日：2018-05-17
发明人： Junli Wang , Veeraraghavan S. Basker , Huiming Bu
IPC分类号： H01L29/66 , H01L21/02 , H01L29/78 , H01L29/417 , H01L21/768
摘要： A method of providing contact surfaces that includes forming a first mask having an opening to a perimeter of a gate electrode, the first mask having a first protecting portion centrally positioned over the gate electrode within the perimeter, and a second protecting portion of the mask is positioned over metal semiconductor alloy surfaces of source and drain contact surfaces; and recessing exposed portions of metal semiconductor alloy and the gate electrode with an etch. In a following step, the method continues with filling the openings provided by recessing the gate perimeter of the gate electrode, recessing the metal semiconductor alloy adjacent to the gate structure, and the recessed gate electrode adjacent to the metal semiconductor alloy surface of the source and drain contact surfaces with a protecting dielectric material.
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公开(公告)号：US11088278B2
公开(公告)日：2021-08-10
申请号：US16245963
申请日：2019-01-11
发明人： Huiming Bu , Liying Jiang , Siyuranga O. Koswatta , Junli Wang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L21/306 , H01L21/02 , H01L29/20 , H01L29/739 , H01L29/165 , H01L29/205
摘要： A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.
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公开(公告)号：US10937867B2
公开(公告)日：2021-03-02
申请号：US16515789
申请日：2019-07-18
IPC分类号： H01L29/76 , H01L29/10 , H01L29/06 , H01L29/66 , H01L21/223 , H01L21/324
摘要： A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.
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公开(公告)号：US20200083088A1
公开(公告)日：2020-03-12
申请号：US16126521
申请日：2018-09-10
发明人： Huimei Zhou , Gen Tsutsui , Andrew M. Greene , Dechao Guo , Huiming Bu , Robert Robison , Veeraraghavan S. Basker , Reinaldo Vega
IPC分类号： H01L21/762 , H01L29/66 , H01L29/78 , H01L21/32
摘要： Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.
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公开(公告)号：US10522636B2
公开(公告)日：2019-12-31
申请号：US16261847
申请日：2019-01-30
发明人： Chun Wing Yeung , Chen Zhang , Peng Xu , Huiming Bu , Kangguo Cheng
IPC分类号： H01L29/417 , H01L29/06 , H01L29/78 , H01L29/66 , H01L29/786
摘要： A method of forming a semiconductor structure includes forming a nanosheet stack disposed over a first portion of a substrate and a fin channel material disposed over a second portion of the substrate, patterning the nanosheet stack disposed over the first portion of the substrate to form two or more nanosheet channels for at least one nanosheet field-effect transistor, patterning the fin channel material disposed over the second portion of the substrate to form one or more fins for at least one fin field-effect transistor, forming a first dielectric layer surrounding the nanosheet channels and the one or more fins, patterning a mask layer over the one or more fins, removing the first dielectric layer surrounding the nanosheet channels, removing the mask layer, forming a second dielectric layer surrounding the nanosheet channels and over the first dielectric layer surrounding the one or more fins, and forming a gate conductive layer over the second dielectric layer.
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公开(公告)号：US10510892B2
公开(公告)日：2019-12-17
申请号：US15395637
申请日：2016-12-30
发明人： Huiming Bu , Kangguo Cheng , Dechao Guo , Sivananda K. Kanakasabapathy , Peng Xu
IPC分类号： H01L21/76 , H01L29/78 , H01L29/66 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/06 , H01L21/3065 , H01L21/324 , H01L21/8234 , H01L21/8238 , H01L21/84
摘要： Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.
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公开(公告)号：US10276558B1
公开(公告)日：2019-04-30
申请号：US15797119
申请日：2017-10-30
发明人： Brent A. Anderson , Huiming Bu , Terence B. Hook , Xuefeng Liu , Junli Wang , Miaomiao Wang
IPC分类号： H01L27/02 , H01L27/12 , H01L29/808 , H01L27/092 , H01L29/06 , H01L29/78
摘要： Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment, forming a first set of semiconductor fins vertically extending from a substrate, and forming a second set of semiconductor fins vertically extending from the substrate, the distance between the first set of fins and the second set of fins defines a length of a junction. Embodiments also include forming a first epitaxy layer on the substrate, and forming a second epitaxy layer atop a portion of the first epitaxy layer, wherein a PN junction is formed between the first epitaxy layer and the second epitaxy layer, wherein a length of the PN junction is defined by the first set of semiconductor fins and the second semiconductor fins. Embodiments include forming a first metal contact atop the first epitaxy layer, and forming a second metal contact atop the second epitaxy layer.
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公开(公告)号：US10211316B2
公开(公告)日：2019-02-19
申请号：US15716690
申请日：2017-09-27
发明人： Brent A. Anderson , Huiming Bu , Terence B. Hook , Fee Li Lie , Junli Wang
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/45 , H01L29/78 , H01L29/08
摘要： A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first source/drain layer, and a plurality of fins each disposed on and in contact with the first source/drain layer. Silicide regions are disposed within a portion of the first source/drain layer. A gate structure is in contact with the plurality of fins, and a second source/drain layer is disposed on the gate structure. The method includes forming silicide in a portion of a first source/drain layer. A first spacer layer is formed in contact with at least the silicide, the first source/drain layer and the plurality of fins. A gate structure is formed in contact with the plurality of fins and the first spacer layer. A second spacer layer is formed in contact with the gate structure and the plurality of fins.
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公开(公告)号：US20180323110A1
公开(公告)日：2018-11-08
申请号：US16038426
申请日：2018-07-18
IPC分类号： H01L21/8234 , H01L29/66 , H01L21/768 , H01L21/311 , H01L21/02 , H01L27/088 , H01L29/417 , H01L21/3213
CPC分类号： H01L21/823475 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/31111 , H01L21/32139 , H01L21/76802 , H01L21/76837 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66636 , H01L29/66795
摘要： A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.
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公开(公告)号：US09947748B2
公开(公告)日：2018-04-17
申请号：US15406218
申请日：2017-01-13
发明人： Huiming Bu , Shogo Mochizuki , Tenko Yamashita
IPC分类号： H01L21/336 , H01L29/10 , H01L29/66 , H01L21/762 , H01L21/3065 , H01L21/308 , H01L29/161 , H01L29/78 , H01L29/06
CPC分类号： H01L29/1054 , H01L21/02107 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02598 , H01L21/02636 , H01L21/30604 , H01L21/3065 , H01L21/308 , H01L21/31 , H01L21/31105 , H01L21/31116 , H01L21/76224 , H01L21/76248 , H01L21/845 , H01L27/1211 , H01L29/0653 , H01L29/0673 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L29/7851
摘要： A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.
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