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公开(公告)号：US10127970B2
公开(公告)日：2018-11-13
申请号：US15465045
申请日：2017-03-21
发明人： John A. Fifield , Dale E. Pontius
IPC分类号： H02M3/07 , G11C11/408 , G11C11/4074 , H02M3/158
摘要： A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.
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公开(公告)号：US20150092478A1
公开(公告)日：2015-04-02
申请号：US14041663
申请日：2013-09-30
发明人： John A. Fifield , Steven J. Kurtz
IPC分类号： G11C11/16 , H03K19/096
CPC分类号： G11C11/1693 , G11C11/161 , G11C11/1675 , G11C11/5607 , H03K19/096
摘要： A nano-magnetic element array having a conductive line adjacent to a group of nano-magnetic elements and a multi-level current driver connected to an input node on the conductive line. The current driver is controlled by a pair of voltage clock signals and a voltage reference so as to selectively change the current amount at the input node between a first level that erases the state of the elements, a second level that switches the state of the elements and a third level that maintains the state of the elements. The current driver is further configured so that the transition from the second to the third level is gradual. Optionally, a bias generator can selectively adjust the voltage reference and thereby, the current amount at the input node. Also, optionally, the same voltage clock signal and voltage reference lines can be used to control multiple multi-level current drivers within the array.
摘要翻译： 具有与一组纳米磁性元件相邻的导线的纳米磁性元件阵列和连接到该导线上的输入节点的多电平电流驱动器。 电流驱动器由一对电压时钟信号和电压基准控制，以便在消除元件状态的第一电平之间选择性地改变输入节点处的电流量，切换元件状态的第二电平 和维持元素状态的第三级别。 进一步配置当前驱动器，使得从第二级到第三级的转换是渐进式的。 可选地，偏置发生器可以选择性地调整电压基准，从而选择性地调整输入节点处的电流量。 此外，可选地，可以使用相同的电压时钟信号和电压参考线来控制阵列内的多个多电平电流驱动器。
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公开(公告)号：US10438652B2
公开(公告)日：2019-10-08
申请号：US16058491
申请日：2018-08-08
发明人： John A. Fifield , Dale E. Pontius
IPC分类号： H02M3/07 , G11C11/408 , G11C11/4074 , H02M3/158
摘要： A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.
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4.发明授权Adjustable reference voltage generator for single-ended DRAM sensing devices 有权用于单端DRAM感测器件的可调参考电压发生器公开(公告)号：US09000837B1
公开(公告)日：2015-04-07
申请号：US14072321
申请日：2013-11-05
发明人： John A. Fifield
CPC分类号： G11C29/028 , G11C11/40 , G11C29/021
摘要： Methods, systems, and structures for generating a target reference voltage are provided. A circuit includes a voltage adjuster, a switch, and a current source. The switch selectively connects the current source to circuit paths in the voltage adjuster. A first of the circuit paths incrementally decreases the target reference voltage with respect to the input voltage. A second of the circuit paths incrementally increases the target voltage with respect to the input voltage.
摘要翻译： 提供了用于产生目标参考电压的方法，系统和结构。 电路包括电压调节器，开关和电流源。 开关选择性地将电流源连接到电压调节器中的电路路径。 电路中的第一路径相对于输入电压递增地降低目标参考电压。 电路中的第二路径相对于输入电压递增地增加目标电压。
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公开(公告)号：US10224932B2
公开(公告)日：2019-03-05
申请号：US15783044
申请日：2017-10-13
发明人： John A. Fifield
IPC分类号： H03L5/00 , H03K19/0185 , H03K19/017 , H03K19/0944
摘要： A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.
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公开(公告)号：US10224710B2
公开(公告)日：2019-03-05
申请号：US15815473
申请日：2017-11-16
IPC分类号： H02H9/00 , H02H9/04 , H01L23/522 , H01L27/02 , H01L29/94
摘要： An electrostatic discharge protection circuit includes a power clamp device, a timing circuit including a first resistor, a first capacitor that is connected with the first resistor at a first node, and a second capacitor that is connected to a second node, a logic gate including a first input connected with the first node, a second input connected with the second node, and an output connected with the power clamp device, and a decoder device connected with a first address pin and a second address pin. The first address pin and the second address pin are used to detect the power clamp device switching on at time of power on and draining current.
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公开(公告)号：US20180097358A1
公开(公告)日：2018-04-05
申请号：US15815464
申请日：2017-11-16
IPC分类号： H02H9/04 , H01L27/02 , H01L23/522 , H01L29/94
CPC分类号： H02H9/046 , H01L23/5228 , H01L27/0285 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection circuit includes a transistor device, a first timing circuit including a first resistor and a first capacitor that is connected with the first resistor at a first node, a second timing circuit including a second resistor and a second capacitor that is connected with the second resistor at a second node, and a logic gate including a first input connected with the first node, a second input coupled with the second node, and an output connected with the transistor device.
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公开(公告)号：US09779783B2
公开(公告)日：2017-10-03
申请号：US14744800
申请日：2015-06-19
CPC分类号： G11C7/065 , G11C17/18 , G11C2207/063
摘要： A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.
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公开(公告)号：US09634557B2
公开(公告)日：2017-04-25
申请号：US14327915
申请日：2014-07-10
发明人： John A. Fifield , Dale E. Pontius
CPC分类号： G11C11/4085 , G11C11/4074 , H02M3/07 , H02M3/158
摘要： A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.
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公开(公告)号：US09093175B2
公开(公告)日：2015-07-28
申请号：US13851202
申请日：2013-03-27
IPC分类号： G11C11/24 , G11C7/00 , G11C5/14 , G11C11/4091 , G11C7/06 , G11C11/4094 , G11C11/4097
CPC分类号： G11C11/4091 , G11C7/067 , G11C11/4094 , G11C11/4097
摘要： Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.
摘要翻译： 用于单端eDRAM读出放大器的信号容限定心的装置和方法。 多个DRAM单元通过第一位线连接到多路复用器的输入侧。 单端读出放大器通过第二位线连接到多路复用器的输出侧。 单端读出放大器具有开关电压。 第二位线被预充电到选定的电压电平。 复用器将来自多个DRAM单元中选定的一个的单元的信号电压传递到第二位线。 所选择的电压电平被选择为使得第一类型的信号电压的接收在第一方向上调节第二位线的电压，并且接收第二类型的信号电压在相反的第二方向上调节第二位线的电压 从第一个方向，围绕开关电压使信号电压居中。
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