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公开(公告)号：US11163715B1
公开(公告)日：2021-11-02
申请号：US16866121
申请日：2020-05-04
摘要： A coarse-grained reconfigurable array accelerator for solving partial differential equations for problems on a regular grid is provided. The regular grid comprises grid cells which are representative for a physical natural environment wherein a list of physical values is associated with each grid cell. The accelerator comprises configurable processing elements in an accelerator-internal grid connected by an accelerator-internal interconnect system and memory arrays comprising memory cells. The memory arrays are connected to the accelerator-internal interconnect system. Selected ones of the memory arrays are positioned within the accelerator corresponding to positions of the grid cells in the physical natural environment. Thereby, each group of the memory cells is adapted for storing the list of physical values of the corresponding grid cell of the physical natural environment.
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公开(公告)号：US20210342286A1
公开(公告)日：2021-11-04
申请号：US16866121
申请日：2020-05-04
摘要： A coarse-grained reconfigurable array accelerator for solving partial differential equations for problems on a regular grid is provided. The regular grid comprises grid cells which are representative for a physical natural environment wherein a list of physical values is associated with each grid cell. The accelerator comprises configurable processing elements in an accelerator-internal grid connected by an accelerator-internal interconnect system and memory arrays comprising memory cells. The memory arrays are connected to the accelerator-internal interconnect system. Selected ones of the memory arrays are positioned within the accelerator corresponding to positions of the grid cells in the physical natural environment. Thereby, each group of the memory cells is adapted for storing the list of physical values of the corresponding grid cell of the physical natural environment.
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公开(公告)号：US10008474B2
公开(公告)日：2018-06-26
申请号：US15206729
申请日：2016-07-11
发明人： Thomas J. Brunschwiler , Andreas Christian Doering , Ronald Peter Luijten , Stefano Sergio Oggioni , Patricia Maria Sagmeister , Martin Leo Schmatz
IPC分类号： H01L29/40 , H01L25/065 , H01L23/498 , H01L23/31 , H01L23/00 , H01L23/367
CPC分类号： H01L25/0655 , H01L23/13 , H01L23/3114 , H01L23/36 , H01L23/367 , H01L23/49805 , H01L23/49838 , H01L24/48 , H01L25/105 , H01L2224/48091 , H01L2224/48225 , H01L2924/00014 , H01L2924/153 , H05K1/145 , H05K3/3442 , H05K3/366 , H05K3/403 , H05K2201/10515 , H05K2201/1053 , H05K2201/10727 , H05K2201/10984 , H05K2203/0228 , H05K2203/143 , H01L2224/45099
摘要： Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.
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