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1.发明授权公开(公告)号：US10741660B2
公开(公告)日：2020-08-11
申请号：US16006173
申请日：2018-06-12
IPC分类号： H01L29/423 , H01L21/311 , H01L21/28 , H01L29/66
摘要： A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.
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公开(公告)号：US10734234B2
公开(公告)日：2020-08-04
申请号：US15845652
申请日：2017-12-18
摘要： The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
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公开(公告)号：US20190371912A1
公开(公告)日：2019-12-05
申请号：US15991128
申请日：2018-05-29
IPC分类号： H01L29/66 , H01L21/762 , H01L21/308 , H01L21/306 , H01L21/027 , H01L21/8234 , H01L27/088 , H01L21/768 , H01L29/78
摘要： A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
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公开(公告)号：US11054250B2
公开(公告)日：2021-07-06
申请号：US15950271
申请日：2018-04-11
IPC分类号： G01B11/27
摘要： An overlay metrology system includes a multi-channel energy unit that selectively operates in a first mode to deliver first photons having a first wavelength to an object under test, and a second mode to deliver second photons to the object under test. The second photons have a second wavelength different from the first wavelength. The overlay metrology system further includes an electronic controller that selectively activates either the first mode or the second mode based at least in part on at least one characteristic of an object under test, and that generates the first protons or the second photons to detect at least one buried structure included in the object under test.
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公开(公告)号：US20190316900A1
公开(公告)日：2019-10-17
申请号：US15950271
申请日：2018-04-11
IPC分类号： G01B11/27
摘要： An overlay metrology system includes a multi-channel energy unit that selectively operates in a first mode to deliver first photons having a first wavelength to an object under test, and a second mode to deliver second photons to the object under test. The second photons have a second wavelength different from the first wavelength. The overlay metrology system further includes an electronic controller that selectively activates either the first mode or the second mode based at least in part on at least one characteristic of an object under test, and that generates the first protons or the second photons to detect at least one buried structure included in the object under test.
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公开(公告)号：US10347540B1
公开(公告)日：2019-07-09
申请号：US15841887
申请日：2017-12-14
IPC分类号： H01L21/8234 , H01L29/66 , H01L21/3213 , H01L29/78 , H01L21/28 , H01L21/8238
摘要： Semiconductor devices and methods of forming the same include forming gate stacks across a semiconductor fin, each gate stack having a gate conductor. An interlayer dielectric is formed between the gate stacks. A protective layer is formed on the interlayer dielectric that leaves the gate stacks exposed. The gate conductor of at least one gate stack is etched away. A dielectric liner is formed in a gap left by the etched gate conductor.
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公开(公告)号：US20190189517A1
公开(公告)日：2019-06-20
申请号：US16244493
申请日：2019-01-10
发明人： John R. Sporre , Siva Kanakasabapathy , Andrew M. Greene , Jeffrey Shearer , Nicole A. Saulnier
IPC分类号： H01L21/8234 , H01L21/8238 , H01L29/78 , H01L29/66 , H01L25/065 , H01L21/02 , H01L27/088
摘要： Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.
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公开(公告)号：US11990342B2
公开(公告)日：2024-05-21
申请号：US17481516
申请日：2021-09-22
CPC分类号： H01L21/28247 , H01L21/28158 , H01L29/517
摘要： The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
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公开(公告)号：US20220005698A1
公开(公告)日：2022-01-06
申请号：US17481516
申请日：2021-09-22
摘要： The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
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公开(公告)号：US20190198327A1
公开(公告)日：2019-06-27
申请号：US16290306
申请日：2019-03-01
CPC分类号： H01L21/28247 , H01L21/28158 , H01L29/517
摘要： The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
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