公开(公告)号：US20250056839A1

公开(公告)日：2025-02-13

申请号：US18231884

申请日：2023-08-09

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  Julien Frougier ,  Ruilong Xie ,  Jingyun Zhang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/775

Abstract: A semiconductor structure is provided that includes a tunable and shared non-conductive layer as part of a gate stack of at least a pair of nanosheet GAA transistors with a shared metal gate electrode. The semiconductor structure has a tunable non-conductive material/gate dielectric area ratio where the non-conductive material is not constrained to a periphery of the nanosheet stack cross section.

公开(公告)号：US20250031440A1

公开(公告)日：2025-01-23

申请号：US18224653

申请日：2023-07-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Domingo Ferrer ,  Jingyun Zhang ,  Teresa J. Wu ,  Utkarsh Bajpai

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor structure, a system, and a method of forming a multi-silicide structure for stacked FETs within the semiconductor. The semiconductor structure may include an NFET. The semiconductor structure may also include a PFET. The semiconductor structure may also include an NFET silicide proximately connected to the NFET, where the NFET silicide is a first material. The semiconductor structure may also include a PFET silicide proximately connected to the PFET, where the PFET silicide is a second material different than the first material. The system may include the semiconductor structure. The method may include forming an NFET silicide proximately connected to an NFET, where the NFET silicide is a first material. The method may also include forming a PFET silicide proximately connected to a PFET, where the PFET silicide is a second material different than the first material.

公开(公告)号：US12136671B2

公开(公告)日：2024-11-05

申请号：US17566875

申请日：2021-12-31

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

公开(公告)号：US20240113162A1

公开(公告)日：2024-04-04

申请号：US17936417

申请日：2022-09-29

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Ruilong Xie ,  Julien Frougier ,  Ruqiang Bao ,  Prabudhya Roy Chowdhury

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Embodiments of the present invention are directed to monolithic stacked field effect transistor (SFET) processing methods and resulting structures having dual middle dielectric isolation (MDI) separation. In a non-limiting embodiment of the invention, a first nanosheet is formed and a second nanosheet is vertically stacked over the first nanosheet. A gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet and a middle dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The middle dielectric isolation structure includes a first middle dielectric isolation layer and a second middle dielectric isolation layer vertically stacked over the first middle dielectric isolation layer. A portion of the gate extends between the first middle dielectric isolation layer and the second middle dielectric isolation layer in the middle dielectric isolation structure.

公开(公告)号：US20240006467A1

公开(公告)日：2024-01-04

申请号：US17853293

申请日：2022-06-29

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Sagarika Mukesh ,  Anthony I. Chou ,  Andrew M. Greene ,  Ruilong Xie ,  Nicolas Jean Loubet ,  Veeraraghavan S. Basker ,  Junli Wang ,  Effendi Leobandung ,  Jingyun Zhang

IPC: H01L49/02 ,  H01L29/06 ,  H01L27/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L28/24 ,  H01L29/0665 ,  H01L27/0629 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor structure that includes a nanosheet logic device (i.e., nFET and/or pFET) co-integrated with a precision middle-of-the-line (MOL) resistor is provided. The precision MOL resistor is located over a nanosheet device and is present in at least one resistor device region of a semiconductor substrate. The at least one resistor device region can include a first resistor device region in which the MOL resistor is optimized for low capacitance and/or a second resistor device region in which the MOL resistor is optimized for low self-heating.

公开(公告)号：US20230335588A1

公开(公告)日：2023-10-19

申请号：US18337074

申请日：2023-06-19

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Ruilong Xie ,  Alexander Reznicek ,  Jingyun Zhang

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L21/0259 ,  H01L29/786 ,  H01L29/66742 ,  B82Y40/00

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack on a substrate. The nanosheet stack includes an alternating sequence of sacrificial nanosheets and channel nanosheets. The sacrificial nanosheets include second nanosheets located between first nanosheets and third nanosheets. The first nanosheets and the third nanosheets have a first germanium concentration that is lower than a second germanium concentration of the second nanosheets. The sacrificial nanosheets are selectively etched and the lower first germanium concentration causes the first nanosheets and the third nanosheets to be etched slower than the second nanosheets creating an indentation region on opposing sides of the nanosheet stack. The indentation region has a narrowing shape towards remaining second nanosheets of the sacrificial nanosheets.

公开(公告)号：US11756960B2

公开(公告)日：2023-09-12

申请号：US17483981

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Takashi Ando ,  Choonghyun Lee

IPC: H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/3115 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/0673 ,  H01L29/408 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.

公开(公告)号：US20230197778A1

公开(公告)日：2023-06-22

申请号：US17557676

申请日：2021-12-21

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Chen Zhang ,  Jingyun Zhang ,  PIETRO MONTANINI

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/0665 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0649 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments herein include semiconductor structures with an active channel stack having an upper field-effect transistor (FET) and a lower FET vertically stacked below the upper FET The semiconductor structure may also include a dummy stub adjacent to the active channel stack, a lower source/drain (S/D) connected to the active channel stack and laterally extended over the dummy stub, and an upper S/D connected to the active channel stack above the lower S/D.

公开(公告)号：US20230187508A1

公开(公告)日：2023-06-15

申请号：US17550724

申请日：2021-12-14

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Jingyun Zhang ,  Reinaldo Vega ,  Alexander Reznicek

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/42392

Abstract: A semiconductor structure includes a source/drain region having a recessed portion. The semiconductor structure further includes a metal contact having a first portion and a second portion. The first portion of the metal contact has a first width and the second portion of the metal contact has a second width greater than the first width. At least a portion of the second portion of the metal contact is disposed in the recessed portion of the source/drain region.

公开(公告)号：US20230178539A1

公开(公告)日：2023-06-08

申请号：US17545501

申请日：2021-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Julien Frougier ,  Sagarika Mukesh ,  Anthony I. Chou ,  Andrew M. Greene ,  Ruilong Xie ,  Veeraraghavan S. Basker ,  Junli Wang ,  Effendi Leobandung ,  Jingyun Zhang ,  Nicolas Loubet

IPC: H01L27/02 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234

CPC classification number: H01L27/0255 ,  H01L27/1207 ,  H01L27/0296 ,  H01L21/84 ,  H01L27/1211 ,  H01L21/823481

Abstract: A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.