公开(公告)号：US10937810B2

公开(公告)日：2021-03-02

申请号：US16541429

申请日：2019-08-15

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/84 ,  H01L29/78

Abstract: Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.

公开(公告)号：US20200083334A1

公开(公告)日：2020-03-12

申请号：US16682361

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Andrew M. Greene ,  John R. Sporre ,  Peng Xu

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: Methods of forming semiconductor devices include forming a lower dielectric layer, to a height below a height of a dummy gate hardmask disposed across multiple device regions, by forming a dielectric fill to the height of a dummy gate and etching the dielectric fill back. A dummy gate structure includes the dummy gate and the dummy gate hardmask. A protective layer is formed on the dielectric layer to the height of the dummy gate hardmask. The dummy gate hardmask is etched back to expose the dummy gate.

公开(公告)号：US10446452B2

公开(公告)日：2019-10-15

申请号：US15489303

申请日：2017-04-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ryan O. Jung ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/66 ,  H01L21/84 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/66 ,  H01L27/12 ,  H01L21/8234

Abstract: A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.

公开(公告)号：US10438972B2

公开(公告)日：2019-10-08

申请号：US15263005

申请日：2016-09-12

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/84

Abstract: Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.

公开(公告)号：US10249533B1

公开(公告)日：2019-04-02

申请号：US15951787

申请日：2018-04-12

Applicant: International Business Machines Corporation

Inventor： Jeffrey Shearer ,  John R. Sporre ,  Nicole A. Saulnier ,  Hyung Joo Shin

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/66 ,  H01L27/088

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate structures spaced apart from each other on a fin, forming an inorganic plug portion on the fin between at least two gate structures of the plurality of gate structures, forming a dielectric layer on the fin and between remaining gate structures of the plurality of gate structures, forming an organic planarizing layer (OPL) on the plurality of gate structures and on the inorganic plug portion, removing a portion of the OPL to expose the inorganic plug portion, selectively removing the inorganic plug portion, and forming a contact on the fin in place of the removed inorganic plug portion.

公开(公告)号：US10242981B2

公开(公告)日：2019-03-26

申请号：US15445107

申请日：2017-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew M. Greene ,  Balasubramanian S. Pranatharthiharan ,  Sivananda K. Kanakasabapathy ,  John R. Sporre

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/308 ,  H01L21/027 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.

公开(公告)号：US10211319B2

公开(公告)日：2019-02-19

申请号：US15633934

申请日：2017-06-27

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Stuart A. Sieg ,  John R. Sporre

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12

Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

公开(公告)号：US20180331194A1

公开(公告)日：2018-11-15

申请号：US16033786

申请日：2018-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Andrew M. Greene ,  John R. Sporre ,  Peng Xu

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/42376 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02271 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66871 ,  H01L29/775 ,  H01L29/785

Abstract: Semiconductor devices include a first dielectric layer formed over a source and drain region. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a flat, non-recessed top surface. A gate stack passes vertically through the first and second dielectric layers to contact the source and drain regions and an underlying substrate.

公开(公告)号：US20180277663A1

公开(公告)日：2018-09-27

申请号：US15469237

申请日：2017-03-24

Applicant: International Business Machines Corporation

Inventor： Balasubramanian S. Pranatharthiharan ,  Pietro Montanini ,  John R. Sporre ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/6653 ,  H01L29/6656

Abstract: A first layer of a first material is deposited on a first structure and a second structure, a surface of the first structure being disposed substantially parallelly to a surface of the second structure in at least one direction. A selectively removable material is deposited over the first layer and removed up to a height of a first step. The first material is removed from a portion of the first layer that is exposed from removing the selectively removable material up to the height of the first step. A remainder of the selectively removable material is removed to expose a second portion of the first layer, the second portion of the first layer forming the first step. A second layer of a second material is deposited on the first structure, the second structure, and the second portion of the first layer, causing a formation of a stepped structure.

公开(公告)号：US10074730B2

公开(公告)日：2018-09-11

申请号：US15008615

申请日：2016-01-28

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/78 ,  H01L29/40 ,  H01L29/775

CPC classification number: H01L29/66742 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.