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公开(公告)号：US20160294396A1
公开(公告)日：2016-10-06
申请号：US15182052
申请日：2016-06-14
CPC分类号： H03K21/023 , H03K21/40
摘要： A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
摘要翻译： 在计算机处理系统的性能计数器电路中配置预分压电路的方法可以包括在被配置为产生性能计数器电路的事件计数的预分压电路上接收第一数量的信号事件。 该方法可以包括以当前事件计数速率为第一数量的信号事件生成事件计数，并且基于在预分频器处接收到第一信号事件数量的速率来确定所发送的信号事件的检测到的事件计数速率 电路。 该方法可以包括确定检测到的事件计数速率大于当前事件计数速率。 响应于确定检测到的事件计数速率大于当前事件计数速率，该方法可以包括增加当前事件计数速率。
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公开(公告)号：US10067672B2
公开(公告)日：2018-09-04
申请号：US14840503
申请日：2015-08-31
IPC分类号： G06F12/02 , G06F3/06 , G06F1/20 , G11C16/10 , G11C5/14 , G11C7/04 , G11C7/24 , G11C29/02 , G11C29/04
摘要： A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.
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公开(公告)号：US20170060423A1
公开(公告)日：2017-03-02
申请号：US14933575
申请日：2015-11-05
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F1/20 , G06F3/0634 , G06F3/0673 , G11C5/143 , G11C7/04 , G11C7/24 , G11C16/10 , G11C29/027 , G11C29/028 , G11C2029/0409
摘要： A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.
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公开(公告)号：US20170060476A1
公开(公告)日：2017-03-02
申请号：US14840503
申请日：2015-08-31
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F1/20 , G06F3/0634 , G06F3/0673 , G11C5/143 , G11C7/04 , G11C7/24 , G11C16/10 , G11C29/027 , G11C29/028 , G11C2029/0409
摘要： A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.
摘要翻译： 监视存储器性能的方法包括根据由控制寄存器中的配置位指示的自适应模式从存储器的两个或多个部分中选择存储器的第一部分; 在第一采样周期期间监视对存储器的选定部分的存储器访问; 根据用于在随后的采样周期中监视存储器的不同部分的自适应模式，从存储器的两个或更多个部分中选择存储器的不同部分; 在随后的采样周期期间监视对存储器的不同部分的存储器访问; 在多个采样周期中记录存储器的每个部分的相应数量的存储器访问; 并产生一个或多个中断以输出关于被监视的存储器访问的数据用于数据分析。
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公开(公告)号：US09515663B2
公开(公告)日：2016-12-06
申请号：US15182052
申请日：2016-06-14
CPC分类号： H03K21/023 , H03K21/40
摘要： A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
摘要翻译： 在计算机处理系统的性能计数器电路中配置预分压电路的方法可以包括在被配置为产生性能计数器电路的事件计数的预分压电路上接收第一数量的信号事件。 该方法可以包括以当前事件计数速率为第一数量的信号事件生成事件计数，并且基于在预分频器处接收到第一信号事件数量的速率来确定所发送的信号事件的检测到的事件计数速率 电路。 该方法可以包括确定检测到的事件计数速率大于当前事件计数速率。 响应于确定检测到的事件计数速率大于当前事件计数速率，该方法可以包括增加当前事件计数速率。
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公开(公告)号：US20160065219A1
公开(公告)日：2016-03-03
申请号：US14472995
申请日：2014-08-29
CPC分类号： H03K21/023 , H03K21/40
摘要： A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
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公开(公告)号：US10831659B2
公开(公告)日：2020-11-10
申请号：US16146687
申请日：2018-09-28
IPC分类号： G06F12/0811 , G06F12/0891 , G06F12/0895 , G06F12/0888
摘要： A method handles cache misses using a Scope Resolution Tag Buffer (SRTB). A cache controller assigns each data block in L2 cache with an n-bit value, where the n-bit value describes a quantity of occurrences in which the data block has been accessed, and where the cache controller increments the n-bit value in one or more data blocks in the first level memory cache each time the one or more data blocks are accessed. The cache controller evicts a particular data block from the L2 cache, and stores a particular data block address where the particular data block is now stored in a Scope Resolution Tag Buffer (SRTB). The information in the SRTB is used to locate which cache or memory contains the particular data block in the event of a subsequent cache miss in the L2 cache.
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公开(公告)号：US10078447B2
公开(公告)日：2018-09-18
申请号：US14933575
申请日：2015-11-05
IPC分类号： G06F12/02 , G06F3/06 , G06F1/20 , G11C16/10 , G11C5/14 , G11C7/04 , G11C7/24 , G11C29/02 , G11C29/04
CPC分类号： G06F3/0604 , G06F1/20 , G06F1/206 , G06F3/0634 , G06F3/0673 , G11C5/143 , G11C7/04 , G11C7/24 , G11C16/10 , G11C29/027 , G11C29/028 , G11C2029/0409
摘要： A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.
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公开(公告)号：US09419625B2
公开(公告)日：2016-08-16
申请号：US14472995
申请日：2014-08-29
CPC分类号： H03K21/023 , H03K21/40
摘要： A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
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